mirror of
https://github.com/bergercookie/asm-lsp.git
synced 2025-12-23 12:26:44 +00:00
3943 lines
297 KiB
HTML
Vendored
3943 lines
297 KiB
HTML
Vendored
<!DOCTYPE html>
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<html lang="en">
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<head>
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<meta charset="utf-8" />
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<title>6502 Instruction Set</title>
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<meta name="description" content="Instruction set of the MOS 6502/6507/6510 MPU" />
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<meta property="og:title" content="6502 Instruction Set" />
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<meta property="og:type" content="website" />
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<meta property="og:url" content="https://www.masswerk.at/6502/6502_instruction_set.html" />
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<meta name="application-name" content="6502 Instruction Set" />
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<meta property="og:description" content="A comprehensive instruction sheet for the MOS 6502 MPU." />
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<meta property="og:image" content="https://www.masswerk.at/6502/MOS-6502-preview.jpg" />
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<meta name="twitter:image" content="https://www.masswerk.at/6502/MOS-6502-preview.jpg" />
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<meta name="format-detection" content="telephone=no" />
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<link rel="stylesheet" href="/webfonts/mplus-1m.css" type="text/css" />
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<link rel="shortcut icon" href="favicon.ico?v=1.1" type="image/x-icon" />
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<link rel="image_src" href="https://www.masswerk.at/6502/MOS-6502-preview.jpg" />
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<script type="text/javascript">
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document.addEventListener('DOMContentLoaded', function() {
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var opcDict = {
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'ADC': 'Add with carry',
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'AND': 'And',
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'ASL': 'Arithmetic shift left',
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'BCC': 'Branch on carry clear',
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'BCS': 'Branch on carry set',
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'BEQ': 'Branch on equal',
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'BIT': 'Bit test',
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'BMI': 'Branch on minus',
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'BNE': 'Branch on not equal',
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'BPL': 'Branch on plus',
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'BRK': 'Break / interrupt',
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'BVC': 'Branch on overflow clear',
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'BVS': 'Branch on overflow set',
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'CLC': 'Clear carry',
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'CLD': 'Clear decimal',
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'CLI': 'Clear interrupt disable',
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'CLV': 'Clear overflow',
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'CMP': 'Compare with accumulator',
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'CPX': 'Compare with X',
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'CPY': 'Compare with Y',
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'DEC': 'Decrement',
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'DEX': 'Decrement X',
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'DEY': 'Decrement Y',
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'EOR': 'Exclusive or',
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'INC': 'Increment',
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'INX': 'Increment X',
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'INY': 'Increment Y',
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'JMP': 'Jump',
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'JSR': 'Jump subroutine',
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'LDA': 'Load accumulator',
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'LDX': 'Load X',
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'LDY': 'Load Y',
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'LSR': 'Logical shift right',
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'NOP': 'No operation',
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'ORA': 'Or with accumulator',
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'PHA': 'Push accumulator onto stack',
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'PHP': 'Push processor status onto stack',
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'PLA': 'Pull accumulator from stack',
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'PLP': 'Pull processor status from stack',
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'ROL': 'Rotate left',
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'ROR': 'Rotate right',
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'RTI': 'Return from interrupt',
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'RTS': 'Return from subroutine',
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'SBC': 'Subtract with carry',
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'SEC': 'Set carry',
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'SED': 'Set decimal',
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'SEI': 'Set interrupt disable',
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'STA': 'Store accumulator',
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'STX': 'Store X',
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'STY': 'Store Y',
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'TAX': 'Transfer accumulator to X',
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'TAY': 'Transfer accumulator to Y',
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'TSX': 'Transfer stack pointer to X',
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'TXA': 'Transfer X to accumulator',
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'TXS': 'Transfer X to stack pointer',
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'TYA': 'Transfer Y to accumulator'
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},
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addrDict = {
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'A': 'accumulator (implied)',
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'abs': 'absolute',
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'abs,X': 'absolute, X-indexed',
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'abs,Y': 'absolute, Y-indexed',
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'#': 'immediate',
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'impl': 'implied',
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'ind': 'indirect',
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'X,ind': 'X-indexed, indirect',
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'ind,Y': 'indirect, Y-indexed',
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'rel': 'relative',
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'zpg': 'zero-page',
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'zpg,X': 'zero-page, X-indexed',
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'zpg,Y': 'zero-page, Y-indexed',
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},
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opcDictIllegals = {
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'ALR': {'label': 'ALR', 'syn': '(ASR)', 'descr': 'AND + LSR' },
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'ANC': {'label': 'ANC', 'syn': '', 'descr': 'AND + set C' },
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'ANC2': {'label': 'ANC', 'syn': '(ANC2)', 'descr': 'AND + set C' },
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'ANE': {'label': 'ANE', 'syn': '(XAA)', 'descr': '* AND X + AND oper' },
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'ARR': {'label': 'ARR', 'syn': '', 'descr': 'AND + ROR' },
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'DCP': {'label': 'DCP', 'syn': '(DCM)', 'descr': 'DEC + CMP' },
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'ISC': {'label': 'ISC', 'syn': '(ISB, INS)', 'descr': 'INC + SBC' },
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'LAS': {'label': 'LAS', 'syn': '(LAR)', 'descr': 'LDA/TSX M' },
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'LAX': {'label': 'LAX', 'syn': '', 'descr': 'LDA + LDX' },
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'LXA': {'label': 'LXA', 'syn': '(LAX)', 'descr': 'LDA + LDX' },
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'RLA': {'label': 'RLA', 'syn': '', 'descr': 'ROL + AND' },
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'RRA': {'label': 'RRA', 'syn': '', 'descr': 'ROR + ADC' },
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'SAX': {'label': 'SAX', 'syn': '(AXS, AAX)', 'descr': 'Store acc. AND X' },
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'SBX': {'label': 'SBX', 'syn': '(AXS, SAX)', 'descr': 'X = (acc. AND X) + SBC' },
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'SHA': {'label': 'SHA', 'syn': '(AHX, AXA)', 'descr': 'Store acc. AND X AND (hi-addr.+1)' },
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'SHX': {'label': 'SHX', 'syn': '(A11, SXA, XAS)', 'descr': 'Store A AND X AND (hi-addr.+1)' },
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'SHY': {'label': 'SHY', 'syn': '(A11, SYA, SAY)', 'descr': 'Store Y AND (hi-addr.+1)' },
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'SLO': {'label': 'SLO', 'syn': '(ASO)', 'descr': 'Store ASL + ORA' },
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'SRE': {'label': 'SRE', 'syn': '(LSE)', 'descr': 'Store LSR + EOR' },
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'TAS': {'label': 'TAS', 'syn': '(XAS, SHS)', 'descr': 'Transfer acc. AND X to SP,\n store acc. AND X and (hi-addr.+1)' },
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'USBC': {'label': 'USBC', 'syn': '(SBC)', 'descr': 'SBC + NOP' },
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'NOPs': {'label': 'NOP', 'syn': '', 'descr': 'No operation' },
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'JAM': {'label': 'JAM', 'syn': '(KIL, HLT)', 'descr': 'Jams the CPU' }
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},
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illegalInstr = {
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0x02: ['JAM', ''],
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0x03: ['SLO', 'X,ind'],
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0x04: ['NOPs', 'zpg'],
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0x07: ['SLO', 'zpg'],
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0x0B: ['ANC', '#'],
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0x0C: ['NOPs', 'abs'],
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0x0F: ['SLO', 'abs'],
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0x12: ['JAM', ''],
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0x13: ['SLO', 'ind,Y'],
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0x14: ['NOPs', 'zpg,X'],
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0x17: ['SLO', 'zpg,X'],
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0x1A: ['NOPs', 'impl'],
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0x1B: ['SLO', 'abs,Y'],
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0x1C: ['NOPs', 'abs,X'],
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0x1F: ['SLO', 'abs,X'],
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0x22: ['JAM', ''],
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0x23: ['RLA', 'X,ind'],
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0x27: ['RLA', 'zpg'],
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0x2B: ['ANC', '#'],
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0x2F: ['RLA', 'abs'],
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0x32: ['JAM', ''],
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0x33: ['RLA', 'ind,Y'],
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0x34: ['NOPs', 'zpg,X'],
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0x37: ['RLA', 'zpg,X'],
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0x3A: ['NOPs', 'impl'],
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0x3B: ['RLA', 'abs,Y'],
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0x3C: ['NOPs', 'abs,X'],
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0x3F: ['RLA', 'abs,X'],
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0x42: ['JAM', ''],
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0x43: ['SRE', 'X,ind'],
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0x44: ['NOPs', 'zpg'],
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0x47: ['SRE', 'zpg'],
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0x4B: ['ALR', '#'],
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0x4F: ['SRE', 'abs'],
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0x52: ['JAM', ''],
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0x53: ['SRE', 'ind,Y'],
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0x54: ['NOPs', 'zpg,X'],
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0x57: ['SRE', 'zpg,X'],
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0x5A: ['NOPs', 'impl'],
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0x5B: ['SRE', 'abs,Y'],
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0x5C: ['NOPs', 'abs,X'],
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0x5F: ['SRE', 'abs,X'],
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0x62: ['JAM', ''],
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0x63: ['RRA', 'X,ind'],
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0x64: ['NOPs', 'zpg'],
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0x67: ['RRA', 'zpg'],
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0x6B: ['ARR', '#'],
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0x6F: ['RRA', 'abs'],
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0x72: ['JAM', ''],
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0x73: ['RRA', 'ind,Y'],
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0x74: ['NOPs', 'zpg,X'],
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0x77: ['RRA', 'zpg,X'],
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0x7A: ['NOPs', 'impl'],
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0x7B: ['RRA', 'abs,Y'],
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0x7C: ['NOPs', 'abs,X'],
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0x7F: ['RRA', 'abs,X'],
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0x80: ['NOPs', '#'],
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0x82: ['NOPs', '#'],
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0x83: ['SAX', 'X,ind'],
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0x87: ['SAX', 'zpg'],
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0x89: ['NOPs', '#'],
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0x8B: ['ANE', '#'],
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0x8F: ['SAX', 'abs'],
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0x92: ['JAM', ''],
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0x93: ['SHA', 'ind,Y'],
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0x97: ['SAX', 'zpg,Y'],
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0x9B: ['TAS', 'abs,Y'],
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0x9C: ['SHY', 'abs,X'],
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0x9E: ['SHX', 'abs,Y'],
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0x9F: ['SHA', 'abs,Y'],
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0xA3: ['LAX', 'X,ind'],
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0xA7: ['LAX', 'zpg'],
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0xAB: ['LXA', '#'],
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0xAF: ['LAX', 'abs'],
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0xB2: ['JAM', ''],
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0xB3: ['LAX', 'ind,Y'],
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0xB7: ['LAX', 'zpg,Y'],
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0xBB: ['LAS', 'abs,Y'],
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0xBF: ['LAX', 'abs,Y'],
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0xC2: ['NOPs', '#'],
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0xC3: ['DCP', 'X,ind'],
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0xC7: ['DCP', 'zpg'],
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0xCB: ['SBX', '#'],
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0xCF: ['DCP', 'abs'],
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0xD2: ['JAM', ''],
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0xD3: ['DCP', 'ind,Y'],
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0xD4: ['NOPs', 'zpg,X'],
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0xD7: ['DCP', 'zpg,X'],
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0xDA: ['NOPs', 'impl'],
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0xDB: ['DCP', 'abs,Y'],
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0xDC: ['NOPs', 'abs,X'],
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0xDF: ['DCP', 'abs,X'],
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0xE2: ['NOPs', '#'],
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0xE3: ['ISC', 'X,ind'],
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0xE7: ['ISC', 'zpg'],
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0xEB: ['USBC', '#'],
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0xEF: ['ISC', 'abs'],
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0xF2: ['JAM', ''],
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0xF3: ['ISC', 'ind,Y'],
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0xF4: ['NOPs', 'zpg,X'],
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0xF7: ['ISC', 'zpg,X'],
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0xFA: ['NOPs', 'impl'],
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0xFB: ['ISC', 'abs,Y'],
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0xFC: ['NOPs', 'abs,X'],
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0xFF: ['ISC', 'abs,X']
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},
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overlay,
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showIllegals = false;
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function OPClickHandler() {
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if (this.classList.contains('undef') && !showIllegals) return;
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var opc = this.getAttribute('data-opc');
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if (opc) {
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if (overlay && overlay.parentNode) overlay.parentNode.removeChild(overlay);
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if (this.blur) this.blur();
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self.location.href = '#' + opc;
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}
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}
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function OPHoverHandler(event) {
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if (this.classList.contains('undef') && !showIllegals) return;
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var descr = this.getAttribute('data-description');
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if (descr) {
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if (event.preventDefault) event.preventDefault();
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event.cancelBubble = true;
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event.returnValue = true;
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if (!overlay) {
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overlay = document.createElement('div');
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overlay.id = 'instrOverlay';
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}
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overlay.style.left = (this.offsetLeft + 4) + 'px';
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overlay.style.top = (this.offsetTop + this.offsetHeight + 4) + 'px';
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overlay.innerHTML = descr + '\n<small>Click for details…</small>';
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this.appendChild(overlay);
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}
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}
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function OPHideHandler(event) {
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if (overlay && overlay.parentNode) overlay.parentNode.removeChild(overlay);
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}
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var rows = document.querySelectorAll('table#opctable tbody tr');
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if (showIllegals) document.querySelector('table#opctable').classList.add('show-illegals');
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for (var r = 0, rl = rows.length; r < rl; r++) {
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var cols = rows[r].getElementsByTagName('td'),
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hi = '$' + '\u200A' + r.toString(16).toUpperCase();
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for (var c = 0, cl = cols.length; c < cl; c++) {
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var el = cols[c],
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inst = hi + c.toString(16).toUpperCase(),
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cn=el.className,
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labe;
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if (!cn) {
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var matches = /^([A-Z]{3})(?:\s(.*))?$/.exec(el.innerHTML);
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if (matches) {
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label = inst + '\nSym.: ' + matches[1] + '\nInstr.: ' + opcDict[matches[1]];
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if (matches[2]) label += '\nAddr.: ' + addrDict[matches[2]];
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el.setAttribute('data-description', label);
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el.setAttribute('aria-label', label.replace(/\n/g, '; '));
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el.setAttribute('data-opc', matches[1]);
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el.className = 'clickable';
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el.addEventListener('click', OPClickHandler, true);
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el.addEventListener('mouseover', OPHoverHandler, true);
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el.addEventListener('mouseout', OPHideHandler, true);
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continue;
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}
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}
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else if (cn=='undef') {
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var data = illegalInstr[(r<<4)|c];
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if (data) {
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var opc = opcDictIllegals[data[0]],
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mode = data[1];
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label = inst + '\nSym.: '+opc.label;
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if (opc.syn) label += ' '+opc.syn;
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label += '\nInstr.: ' + opc.descr;
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if (data[1]) label += '\nAddr.: ' + addrDict[data[1]];
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el.setAttribute('data-description', label);
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el.setAttribute('data-opc', data[0]);
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el.setAttribute('data-label', opc.label+' '+data[1]);
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if (showIllegals) {
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el.innerHTML=opc.label+' '+mode;
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el.setAttribute('aria-label', label.replace(/\n/g, '; '));
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}
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el.addEventListener('click', OPClickHandler, true);
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el.addEventListener('mouseover', OPHoverHandler, true);
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el.addEventListener('mouseout', OPHideHandler, true);
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}
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continue;
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}
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el.setAttribute('data-description', inst);
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}
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}
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rows = null;
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document.querySelector('table#opctable').addEventListener('click', OPHideHandler, false);
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var cbxShowIllegals=document.querySelector('#cbxShowIllegals');
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cbxShowIllegals.checked=showIllegals;
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cbxShowIllegals.addEventListener('change', function(event) {
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showIllegals = !showIllegals;
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var undefs = document.querySelectorAll('table#opctable td.undef');
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for (var i = 0, l = undefs.length; i < l; i++) {
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var el = undefs[i],
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opc = el.getAttribute('data-label'),
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descr = this.getAttribute('data-description');
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if (opc) {
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el.innerHTML = showIllegals? opc : '---';
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}
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if (descr && showIllegals) el.setAttribute('aria-label', descr.replace(/\n/g, '; '));
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else el.removeAttribute('aria-label');
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}
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var table = document.querySelector('table#opctable');
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if (showIllegals) table.classList.add('show-illegals');
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else table.classList.remove('show-illegals');
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}, false);
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}, false);
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// create a target for sibling apps
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window.name='at_masswerk_6502_instset';
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window.addEventListener('unload', function() { window.name=''; }, false);
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</script>
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<style type="text/css">
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body { color: #000; margin: 0; }
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main {
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width: 1020px;
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margin: 1em auto;
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padding: 0 1em;
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overflow: visible;
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box-sizing: content-box;
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}
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h1 { font-family: arial,helvetica,sans-serif; font-size: 24px; margin-bottom: 0.3em; }
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h2 {
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font-family: courier,monospace; font-size: 16px;
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font-weight: bold;
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margin: 4em 0 1.5em 0;
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}
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h2.narrow-margin { margin: 3em 0 1em 0; }
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table { border-collapse: collapse; position: relative;}
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p,td,th,xmp,pre,dt,dd,li { font-family: courier,monospace; font-size: 11px; }
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p { line-height: 1.4; white-space: nowrap; margin: 1em 0; }
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h3,h4 { font-family: courier,monospace; line-height: 1.4; }
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h3 { font-size: 13px; font-weight: bold; margin: 3em 0 1em 0; }
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h4 { font-size: 12px; font-weight: normal; margin: 2em 0 0.5em 0; }
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h2 + h3 { margin-top: 0; }
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figure { margin: 1em 1.5em; }
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figure img { max-width: 100%; height: auto; }
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figure figcaption,
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figure p { margin: 0.5em 1.5em; font-style: italic; font-family: courier,monospace; font-size: 11px; }
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figure.operations { margin: 2em 1.5em; }
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figure.operations figcaption { margin: 1em 1.5em; }
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table#opctable, table#opctable td, table#opctable th {
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border: #888 1px solid;
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}
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table#opctable td, table#opctable th { padding: 5px; min-width: 4em; }
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table#opctable th {
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white-space: nowrap;
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text-align: center;
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vertical-align: top;
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font-style: italic;
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font-weight: normal;
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padding: 5px;
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}
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table#opctable .hi-nibble { background-color: #a6d4df; color: #222; }
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table#opctable .lo-nibble { background-color: #fbebaf; color: #222; }
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table#opctable th.blank { background-color: #a6d4df !important; }
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|
table#opctable th[scope=row] { font-style: normal; padding: 5px 0; }
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|
table#opctable tr.lo-nibble th { font-style: normal; }
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table#opctable thead tr.nibbles { background-color: #ebd1be; }
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|
table#opctable thead tr.low-bits th { background-color: #a7d99b; font-style: normal; }
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table#opctable td.undef { color: #fcf0c3; cursor: default; background-color: #fcf0c3; }
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table#opctable td.clickable { cursor: pointer; }
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|
table#opctable td.clickable:hover,
|
|
table#opctable td.clickable:focus { background-color: royalblue; color: white !important; }
|
|
table#opctable td.clickable:active { background-color: red; color: white; }
|
|
table#opctable td, table#addressmodes td { white-space: nowrap; vertical-align: top; }
|
|
|
|
table#opctable.show-illegals td.undef { background-color: #e8ebec; color: #222223; cursor: pointer; }
|
|
table#opctable.show-illegals td.undef:hover,
|
|
table#opctable.show-illegals td.undef:focus { background-color: royalblue; color: white !important; }
|
|
table#opctable.show-illegals td.undef:active { background-color: red; color: white; }
|
|
|
|
table#addressmodes { margin-bottom: 1.6em; }
|
|
table#addressmodes th { font-style: normal; font-weight: normal; text-align: left; }
|
|
table#addressmodes tr td { padding: 3px; border: none; border-width: 0; }
|
|
table#addressmodes tr td:nth-child(2):before { content: '.... '; display: inline; }
|
|
table#addressmodes tr td:nth-child(2) { padding-left: 7px; }
|
|
table#addressmodes tr td:nth-child(3),
|
|
table#addressmodes tr td:nth-child(4)
|
|
{ padding-left: 15px; }
|
|
table#addressmodes td.semantics { font-style: italic; }
|
|
|
|
table#addressmodes th, table#register td, table#flags td { padding: 3px; border: none; border-width: 0; }
|
|
|
|
dl.opclist { margin: 0; }
|
|
dl.opclist a:link, dl#opclist a:visited { color: #0000a6; text-decoration-style: dotted; }
|
|
dl.opclist a:hover,
|
|
dl.opclist a:focus { color: #00e; text-decoration-style: solid; }
|
|
dl.opclist a:active { color: #e00; text-decoration-style: solid; }
|
|
dl.opclist dt, dl.opclist dd { padding: 3px; border: none; border-width: 0; margin: 0; vertical-align: top; }
|
|
dl.opclist dt { float: left; font-weight: normal; font-style: normal; }
|
|
dl.opclist dt:after { content: '.... '; display: inline; padding-left: 0.55em; }
|
|
dl.opclist dt { white-space: nowrap; width: 4.5em; max-width: 4.5em; overflow-x: hidden; margin-right: 0.5em; }
|
|
dl.opclist.wide dt:after,dl.opclist.xwide dt:after { content: '............. '; white-space: nowrap; }
|
|
dl.opclist.wide dt { width: 7.5em; max-width: 7.5em; }
|
|
dl.opclist.xwide dt { width: 8.5em; max-width: 8.5em; }
|
|
|
|
table#registers tr td:nth-child(2):before,
|
|
table#flags tr td:nth-child(2):before
|
|
{ content: '.... '; display: inline; padding-left: 3px; margin-right: -1px; }
|
|
table#registers tr td:nth-child(3) { padding-left: 0.4em; }
|
|
|
|
dl.opcodes { margin: 0 0 2.4em 0; }
|
|
dl.opcodes dt
|
|
{
|
|
float: left;
|
|
font-weight: normal;
|
|
font-style: normal;
|
|
width: 3em;
|
|
vertical-align: top;
|
|
clear: left;
|
|
margin: 0; padding: 0;
|
|
line-height: 130%;
|
|
}
|
|
dl.opcodes dd { margin: 0 0 2em 3em; vertical-align: top; line-height: 130%; }
|
|
dl.opcodes p[aria-label=summary] { margin: 0 0 1em 0; line-height: 130%; }
|
|
dl.opcodes p[aria-label='notes on the implementation'], dl.opcodes p[aria-label=notes] { margin: 1em 0; line-height: 130%; }
|
|
dl.opcodes p[aria-label=synopsis] { float: left; margin: 0 0 1em 0; width: 20em; line-height: 130%; white-space: nowrap; }
|
|
dl.opcodes table[aria-label=flags] th,
|
|
dl.opcodes table[aria-label=flags] td
|
|
{
|
|
padding: 0;
|
|
width: 1.2em;
|
|
font-weight: normal;
|
|
font-style: normal;
|
|
text-align: center;
|
|
line-height: 130%;
|
|
white-space: nowrap;
|
|
}
|
|
dl.opcodes table[aria-label=details] { clear: left; margin: 1em 0; }
|
|
dl.opcodes table[aria-label=details] th,
|
|
dl.opcodes table[aria-label=details] td
|
|
{
|
|
padding: 0;
|
|
font-weight: normal;
|
|
font-style: normal;
|
|
text-align: left;
|
|
white-space: nowrap;
|
|
line-height: 130%;
|
|
white-space: nowrap;
|
|
}
|
|
dl.opcodes table[aria-label=details] tr:first-child { border-bottom: 1px #000 dashed; }
|
|
dl.opcodes table[aria-label=details] th { padding-top: 0.3em; }
|
|
dl.opcodes table[aria-label=details] tr:nth-child(2) td { padding-top: 0.3em; }
|
|
dl.opcodes table[aria-label=details] tr > *:nth-child(1) { width: 8.5em; }
|
|
dl.opcodes table[aria-label=details] tr > *:nth-child(2) { width: 7.5em; }
|
|
dl.opcodes table[aria-label=details] tr > *:nth-child(3) { width: 3em; text-align: center; }
|
|
dl.opcodes table[aria-label=details] tr > *:nth-child(4) { width: 4.5em; text-align: center; }
|
|
dl.opcodes table[aria-label=details] tr > *:nth-child(5) { width: 3em; text-align: right; white-space: pre; }
|
|
|
|
dl.opcodes.illegals dt { float: none; display: block; margin: 0 0 0.5em 0; width: auto; }
|
|
dl.opcodes.illegals p[aria-label=synopsis] { float: none; margin-bottom: 0; }
|
|
dl.opcodes.illegals p[aria-label=summary] { max-width: 36em; white-space: normal; }
|
|
dl.opcodes.illegals p[aria-label=notes] { max-width: 36em; white-space: normal; }
|
|
|
|
dl.opcodes.illegals table.nops[aria-label=details] tr:first-child { border-bottom: 1px #000 dashed; }
|
|
dl.opcodes.illegals table.nops[aria-label=details] th { padding-bottom: 0.3em; }
|
|
dl.opcodes.illegals table.nops[aria-label=details] tr:nth-child(2) td { padding-top: 0.3em; }
|
|
dl.opcodes.illegals table.nops[aria-label=details] tr > *:nth-child(1) { width: 1.5em; text-align: center; padding-right: 2em; }
|
|
dl.opcodes.illegals table.nops[aria-label=details] tr > *:nth-child(2) { width: 7.5em; }
|
|
dl.opcodes.illegals table.nops[aria-label=details] tr > *:nth-child(3) { width: 4.5em; text-align: center; }
|
|
dl.opcodes.illegals table.nops[aria-label=details] tr > *:nth-child(4) { width: 4.5em; text-align: right; white-space: pre; }
|
|
|
|
dl.opcodes.illegals table[aria-label=details] tr > *:nth-child(6), .warn { color: #a00; }
|
|
|
|
dl.opcodes.illegals table[aria-label=flags] { margin: 0.3em 0 0 19.5em; }
|
|
|
|
a.footnote:link, a.footnote:visited { color: #0000a6; }
|
|
a.footnote { text-decoration: none; }
|
|
a.footnote:hover,
|
|
a.footnote:focus { text-decoration: underline; color: #00e;}
|
|
a.footnote:active { text-decoration: underline; color: #e00; }
|
|
|
|
dl.footnotes { margin: 1.2em 0; }
|
|
dl.footnotes dd { margin: 0 0 0.5em 3em; vertical-align: top; line-height: 130%; }
|
|
dl.footnotes dt
|
|
{
|
|
float: left;
|
|
font-weight: normal;
|
|
font-style: normal;
|
|
width: 3em;
|
|
vertical-align: top;
|
|
clear: left;
|
|
margin: 0 0 0.5em 0;
|
|
padding: 0 0 0 0.2em;
|
|
line-height: 130%;
|
|
box-sizing: border-box;
|
|
}
|
|
dl.footnotes-opcodes { margin: 2.4em 0 1.2em 0; }
|
|
dl.footnotes-opcodes dt { padding-left: 0.6em; }
|
|
dl.footnotes-opcodes.illegals { margin: 0 0 2em 0; }
|
|
|
|
p.opcodes-legend { float: left; width: 7.5em; margin: 0; line-height: 130%; }
|
|
dl.opcodes-legend-list { margin: 0 0 1.2em 7.5em; }
|
|
dl.opcodes-legend-list dt, dl.opcodes-legend-list dd { margin: 0; }
|
|
dl.opcodes-legend-list dt { width: 1.2em; clear: none; }
|
|
dl.opcodes-legend-list dd:before { content: '.... '; display: inline; padding-left: 0.4em; }
|
|
.illegals-remarks p { max-width: 48em; white-space: normal; }
|
|
|
|
div.instrlayout-wrapper {
|
|
display: table;
|
|
border: #888 1px dotted;
|
|
padding: 7px 3px 3px 3px;
|
|
margin: 1.75em 0;
|
|
}
|
|
table.instrlayout { margin: 0; }
|
|
table.instrlayout td,
|
|
table.instrlayout th[scope=rowgroup],table.instrlayout th[scope=row]
|
|
{ border-left: #fff 2px solid; border-right: #fff 2px solid; border-top: #fff 1px solid; border-bottom: #fff 1px solid; font-style: normal; vertical-align: middle; padding: 7px 5px; }
|
|
table.instrlayout tr.g-first > *:first-child,
|
|
table.instrlayout tr.g-last > * { border-bottom: #fff 2px solid; }
|
|
table.instrlayout tr.g-first > *:first-child,
|
|
table.instrlayout tr.g-first > * { border-top: #fff 2px solid; }
|
|
table.instrlayout tr.t-half-top > *:first-child,
|
|
table.instrlayout tr.t-half-top > * { border-bottom: #fff 4px solid; }
|
|
table.instrlayout tr.t-half-bottom > *:first-child,
|
|
table.instrlayout tr.t-half-bottom > * { border-top: #fff 4px solid; }
|
|
table.instrlayout th {
|
|
white-space: nowrap;
|
|
text-align: center;
|
|
vertical-align: bottom;
|
|
font-style: italic;
|
|
font-weight: normal;
|
|
padding: 0 5px 5px 5px;
|
|
}
|
|
table.instrlayout tr.bn th { font-style: normal; font-weight: bold; }
|
|
table.instrlayout span.opc { color: rgba(0,0,0, 0.6); margin-right: 1.25em; }
|
|
table.instrlayout *.a-b { width: 6em; text-align: center; font-weight: bold; }
|
|
table.instrlayout tr.r-even > *.a { background-color: #8bcd7b; }
|
|
table.instrlayout tr.r-odd > *.a { background-color: #a7d99b; }
|
|
table.instrlayout tr.r-even > *.b { background-color: #d7a580; }
|
|
table.instrlayout tr.r-odd > *.b { background-color: #e0bb9e; }
|
|
table.instrlayout tr > *.c { width: 5em; text-align: center; font-weight: bold; }
|
|
table.instrlayout tr > *.c0 { background-color: #6ab7c9; }
|
|
table.instrlayout tr > *.c1 { background-color: #88c5d4; }
|
|
table.instrlayout tr > *.c2 { background-color: #a6d4df; }
|
|
table.instrlayout tr > *.c3 { background-color: #c6e3ea; }
|
|
table.instrlayout tr > *.v0,
|
|
table.instrlayout tr > *.v1,
|
|
table.instrlayout tr > *.v2,
|
|
table.instrlayout tr > *.v3,
|
|
table.instrlayout tr > *.v4,
|
|
table.instrlayout tr > *.v5,
|
|
table.instrlayout tr > *.v6,
|
|
table.instrlayout tr > *.v7 { min-width: 8.5em; }
|
|
table.instrlayout tr.r0 > *.v0,
|
|
table.instrlayout tr.r0 > *.v2,
|
|
table.instrlayout tr.r0 > *.v4,
|
|
table.instrlayout tr.r0 > *.v6 { background-color: #f7d866; }
|
|
table.instrlayout tr.r1 > *.v0,
|
|
table.instrlayout tr.r1 > *.v2,
|
|
table.instrlayout tr.r1 > *.v4,
|
|
table.instrlayout tr.r1 > *.v6 { background-color: #f9e085; }
|
|
table.instrlayout tr.r2 > *.v0,
|
|
table.instrlayout tr.r2 > *.v2,
|
|
table.instrlayout tr.r2 > *.v4,
|
|
table.instrlayout tr.r2 > *.v6 { background-color: #fae8a3; }
|
|
table.instrlayout tr.r0 > *.v1,
|
|
table.instrlayout tr.r0 > *.v3,
|
|
table.instrlayout tr.r0 > *.v5,
|
|
table.instrlayout tr.r0 > *.v7 { background-color: #fae69b; }
|
|
table.instrlayout tr.r1 > *.v1,
|
|
table.instrlayout tr.r1 > *.v3,
|
|
table.instrlayout tr.r1 > *.v5,
|
|
table.instrlayout tr.r1 > *.v7 { background-color: #fbebaf; }
|
|
table.instrlayout tr.r2 > *.v1,
|
|
table.instrlayout tr.r2 > *.v3,
|
|
table.instrlayout tr.r2 > *.v5,
|
|
table.instrlayout tr.r2 > *.v7 { background-color: #fcf0c3; }
|
|
|
|
table.instrlayout tr.r1 > *.v0.illegal,
|
|
table.instrlayout tr.r1 > *.v2.illegal,
|
|
table.instrlayout tr.r1 > *.v4.illegal,
|
|
table.instrlayout tr.r1 > *.v6.illegal { background-color: #dfe1e2; }
|
|
table.instrlayout tr.r1 > *.v1.illegal,
|
|
table.instrlayout tr.r1 > *.v3.illegal,
|
|
table.instrlayout tr.r1 > *.v5.illegal,
|
|
table.instrlayout tr.r1 > *.v7.illegal { background-color: #e9eced; }
|
|
table.instrlayout tr.r3 > *.v0.illegal,
|
|
table.instrlayout tr.r3 > *.v1.illegal,
|
|
table.instrlayout tr.r3 > *.v2.illegal,
|
|
table.instrlayout tr.r3 > *.v3.illegal,
|
|
table.instrlayout tr.r3 > *.v4.illegal,
|
|
table.instrlayout tr.r3 > *.v5.illegal,
|
|
table.instrlayout tr.r3 > *.v6.illegal,
|
|
table.instrlayout tr.r3 > *.v7.illegal { background-color: #eef0f1; }
|
|
table.instrlayout tr.r0 > *.v0.illegal,
|
|
table.instrlayout tr.r0 > *.v1.illegal,
|
|
table.instrlayout tr.r0 > *.v2.illegal,
|
|
table.instrlayout tr.r0 > *.v3.illegal,
|
|
table.instrlayout tr.r0 > *.v4.illegal,
|
|
table.instrlayout tr.r0 > *.v5.illegal,
|
|
table.instrlayout tr.r0 > *.v6.illegal,
|
|
table.instrlayout tr.r0 > *.v7.illegal { background-color: #e0e3e4; }
|
|
table.instrlayout tr.r2 > *.v0.illegal,
|
|
table.instrlayout tr.r2 > *.v1.illegal,
|
|
table.instrlayout tr.r2 > *.v2.illegal,
|
|
table.instrlayout tr.r2 > *.v3.illegal,
|
|
table.instrlayout tr.r2 > *.v4.illegal,
|
|
table.instrlayout tr.r2 > *.v5.illegal,
|
|
table.instrlayout tr.r2 > *.v6.illegal,
|
|
table.instrlayout tr.r2 > *.v7.illegal { background-color: #e5e8e9; }
|
|
table.instrlayout td.illegal { color: #222223; }
|
|
|
|
table.instrlayout tr.a th { background-color: #c6e6be; }
|
|
table.instrlayout tr.b th { background-color: #ebd3c0; }
|
|
table.instrlayout tr.c th { background-color: #c5e3ea; }
|
|
table.instrlayout tr.b0 th { background-color: #e8ccb6; }
|
|
table.instrlayout tr.a th:nth-child(odd) { background-color: #b3dea9; }
|
|
table.instrlayout tr.b th:nth-child(odd) { background-color: #e5c4ac; }
|
|
table.instrlayout tr.c th:nth-child(odd) { background-color: #9ed0dc; }
|
|
table.instrlayout thead th[scope=col] { vertical-align: top; }
|
|
table.instrlayout thead th { padding: 0 3px 3px 3px; }
|
|
table.instrlayout thead tr.bn th[scope=col] { padding: 3px; border-left: 2px #fff solid; border-right: 2px #fff solid; }
|
|
|
|
table.instrvector { margin: 1em 0.5em; }
|
|
table.instrvector td, table.instrvector th { padding: 4px; text-align: center; white-space: nowrap; font-style: normal; font-weight: normal; }
|
|
table.instrvector td.a, table.instrvector td.b, table.instrvector td.c { border: 1px #888 solid; }
|
|
table.instrvector td.a { background-color: #a7d99b; }
|
|
table.instrvector td.b { background-color: #e0bb9e; }
|
|
table.instrvector td.c { background-color: #a6d4df; }
|
|
table.instrvector th.legend { text-align: left; width: 2.5em; }
|
|
table.instrvector tr.range td { padding: 0; font-size: 10px; color: #222; }
|
|
|
|
div.explanation { margin: 0; }
|
|
div.explanation p, p.explanation { font-size: 12px; }
|
|
|
|
table#mpus { margin: 0 0 0 0.8em; }
|
|
table#mpus tr > * { font-style: normal; font-weight: normal; line-height: 140%; padding: 0; text-align: left; }
|
|
table#mpus th { padding-bottom: 0.4em; border-bottom: 1px #000 dashed; }
|
|
table#mpus tbody tr:first-child td { padding-top: 0.4em; }
|
|
table#mpus tr > *:first-child { vertical-align: top; padding-right: 1.25em; white-space: nowrap; }
|
|
|
|
ul.links { margin: -0.6em 0 1em 0; padding: 0 0 0 0.8em; list-style-type: '>>'; }
|
|
ul.links li { margin: 0; padding: 0 0 0 0.4em; line-height: 160%; }
|
|
|
|
ul.flow { margin: 0.5em 0; padding-left: 1.125em; line-height: 1.4; }
|
|
ul.flow li { margin-bottom: 0.5em; }
|
|
ul.flow a:link { color: #0000a6; text-decoration: none; }
|
|
ul.flow a:hover,
|
|
ul.flow a:focus { color: #00e; text-decoration: underline; }
|
|
ul.flow a:active { color: #e00; text-decoration: underline; }
|
|
ul.flow.narrow { margin: 1em 0; padding-left: 1.5em; }
|
|
ul.flow.narrow li { margin-bottom: 0.4em; }
|
|
|
|
table.compare { margin: 1.25em 0.25em; }
|
|
table.compare th,
|
|
table.compare td { text-align: left; white-space: nowrap; font-size: 13px; }
|
|
table.compare th + th,
|
|
table.compare td + td { padding-left: 2em; }
|
|
table.compare th { font-weight: normal; font-style: normal; padding-bottom: 0.4em; border-bottom: 1px #000 dashed; }
|
|
table.compare tbody tr:first-child td { padding-top: 0.4em; }
|
|
table.compare a:link, table.compare a:visited { color: #0000a6; text-decoration-style: dotted; }
|
|
table.compare a:hover,
|
|
table.compare a:focus { color: #00e; text-decoration-style: solid; }
|
|
table.compare a:active { color: #e00; text-decoration-style: solid; }
|
|
|
|
a span.dotted { text-decoration: underline; text-decoration-style: dotted; }
|
|
a:hover span.dotted,
|
|
a:focus span.dotted,
|
|
a:active span.dotted { text-decoration-style: solid; }
|
|
|
|
ul.bytypelist { padding-left: 0.75em; }
|
|
ul.bytypelist h4 { font-weight: bold; }
|
|
ul.bytypelist p { width: 450px; max-width: 100%; white-space: normal; }
|
|
|
|
ul.flaglist,ul.wdc { padding-left: 0.75em; }
|
|
ul.flaglist li
|
|
{
|
|
width: 450px; max-width: 100%;
|
|
white-space: normal;
|
|
font-size: 12px;
|
|
line-height: 1.4;
|
|
margin-bottom: 0.5em;
|
|
}
|
|
ul.wdc li
|
|
{
|
|
width: 550px; max-width: 100%;
|
|
white-space: normal;
|
|
font-size: 12px;
|
|
line-height: 1.4;
|
|
margin-bottom: 0.5em;
|
|
}
|
|
|
|
table.comparison
|
|
{
|
|
border-collapse: collapse;
|
|
margin: 1em 0 1.5em 0.25em;
|
|
}
|
|
table.comparison td
|
|
{
|
|
padding: 0.5em 0.75em;
|
|
border: 1px #555 solid;
|
|
}
|
|
|
|
ul.nav
|
|
{
|
|
list-style: none;
|
|
padding: 0 0 0 0.25em;
|
|
margin: 0 0 1em 0;
|
|
}
|
|
ul.nav.toc { margin: 0 0 0.25em 0; padding-left: 2.25rem; }
|
|
ul.nav li
|
|
{
|
|
display: inline-block;
|
|
margin: 0;
|
|
}
|
|
ul.toc li:first-child { position: relative; }
|
|
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}
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hr { max-width: 50%; margin: 3.5em auto; height: 0; border: 0; border-top: 1px dotted #777; }
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@page { size:landscape; }
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</style>
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</head>
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<body>
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<main>
|
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<h1>6502 Instruction Set</h1>
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|
|
<ul class="nav toc" role="navigation" aria-label="Table of Contents">
|
|
<li><a href="#description">Description</a></li>
|
|
<li><a href="#bytype">Instructions by Type</a></li>
|
|
<li><a href="#modes">Address Modes in Detail</a></li>
|
|
<li><a href="#details">Instructions in Detail</a></li>
|
|
<li><a href="#illegals">"Illegal" Opcodes</a></li>
|
|
<li><a href="#compare">Comparisons</a></li>
|
|
<li><a href="#arithmetic">A Primer of 6502 Arithmetic Operations</a></li>
|
|
<li><a href="#stack">Jump Vectors and Stack Operations</a></li>
|
|
<li><a href="#layout">Instruction Layout</a></li>
|
|
<li><a href="#pinout">Pinout</a></li>
|
|
<li><a href="#family">65xx-Family</a></li>
|
|
</ul>
|
|
<ul class="nav tools" role="navigation" aria-label="Related Tools">
|
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<li><a href="./" target="at_masswerk_6502_virtual6502">6502 Emulator</a></li>
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<li><a href="assembler.html" target="at_masswerk_6502_assembler">6502 Assembler</a></li>
|
|
<li><a href="disassembler.html" target="at_masswerk_6502_disassembler">6502 Disassembler</a></li>
|
|
</ul>
|
|
|
|
<table id="opctable" aria-label="table of instruction codes">
|
|
<colgroup>
|
|
<col class="hi-nibble"/>
|
|
<col span="16" class="lo-nibble"/>
|
|
</colgroup>
|
|
<thead>
|
|
<tr class="nibbles">
|
|
<th scope="col" aria-label="first column: high-nibble of byte (hexadecimal)">HI</th><th colspan="16" aria-label="columns 1 - 16: low nibble (hexadecimal)">LO-NIBBLE</th>
|
|
</tr>
|
|
<tr class="low-bits">
|
|
<th class="blank"> </th><th scope="col">‐0</th><th scope="col">‐1</th><th scope="col">‐2</th><th scope="col">‐3</th><th scope="col">‐4</th><th scope="col">‐5</th><th scope="col">‐6</th><th scope="col">‐7</th><th scope="col">‐8</th><th scope="col">‐9</th><th scope="col">‐A</th><th scope="col">‐B</th><th scope="col">‐C</th><th scope="col">‐D</th><th scope="col">‐E</th><th scope="col">‐F</th></tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<th scope="row">0‐</th><td>BRK impl</td><td>ORA X,ind</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>ORA zpg</td><td>ASL zpg</td><td class="undef">---</td><td>PHP impl</td><td>ORA #</td><td>ASL A</td><td class="undef">---</td><td class="undef">---</td><td>ORA abs</td><td>ASL abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">1‐</th><td>BPL rel</td><td>ORA ind,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>ORA zpg,X</td><td>ASL zpg,X</td><td class="undef">---</td><td>CLC impl</td><td>ORA abs,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>ORA abs,X</td><td>ASL abs,X</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">2‐</th><td>JSR abs</td><td>AND X,ind</td><td class="undef">---</td><td class="undef">---</td><td>BIT zpg</td><td>AND zpg</td><td>ROL zpg</td><td class="undef">---</td><td>PLP impl</td><td>AND #</td><td>ROL A</td><td class="undef">---</td><td>BIT abs</td><td>AND abs</td><td>ROL abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">3‐</th><td>BMI rel</td><td>AND ind,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>AND zpg,X</td><td>ROL zpg,X</td><td class="undef">---</td><td>SEC impl</td><td>AND abs,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>AND abs,X</td><td>ROL abs,X</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">4‐</th><td>RTI impl</td><td>EOR X,ind</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>EOR zpg</td><td>LSR zpg</td><td class="undef">---</td><td>PHA impl</td><td>EOR #</td><td>LSR A</td><td class="undef">---</td><td>JMP abs</td><td>EOR abs</td><td>LSR abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">5‐</th><td>BVC rel</td><td>EOR ind,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>EOR zpg,X</td><td>LSR zpg,X</td><td class="undef">---</td><td>CLI impl</td><td>EOR abs,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>EOR abs,X</td><td>LSR abs,X</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">6‐</th><td>RTS impl</td><td>ADC X,ind</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>ADC zpg</td><td>ROR zpg</td><td class="undef">---</td><td>PLA impl</td><td>ADC #</td><td>ROR A</td><td class="undef">---</td><td>JMP ind</td><td>ADC abs</td><td>ROR abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">7‐</th><td>BVS rel</td><td>ADC ind,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>ADC zpg,X</td><td>ROR zpg,X</td><td class="undef">---</td><td>SEI impl</td><td>ADC abs,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>ADC abs,X</td><td>ROR abs,X</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">8‐<td class="undef">---</td><td>STA X,ind</td><td class="undef">---</td><td class="undef">---</td><td>STY zpg</td><td>STA zpg</td><td>STX zpg</td><td class="undef">---</td><td>DEY impl</td><td class="undef">---</td><td>TXA impl</td><td class="undef">---</td><td>STY abs</td><td>STA abs</td><td>STX abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">9‐</th><td>BCC rel</td><td>STA ind,Y</td><td class="undef">---</td><td class="undef">---</td><td>STY zpg,X</td><td>STA zpg,X</td><td>STX zpg,Y</td><td class="undef">---</td><td>TYA impl</td><td>STA abs,Y</td><td>TXS impl</td><td class="undef">---</td><td class="undef">---</td><td>STA abs,X</td><td class="undef">---</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">A‐</th><td>LDY #</td><td>LDA X,ind</td><td>LDX #</td><td class="undef">---</td><td>LDY zpg</td><td>LDA zpg</td><td>LDX zpg</td><td class="undef">---</td><td>TAY impl</td><td>LDA #</td><td>TAX impl</td><td class="undef">---</td><td>LDY abs</td><td>LDA abs</td><td>LDX abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">B‐</th><td>BCS rel</td><td>LDA ind,Y</td><td class="undef">---</td><td class="undef">---</td><td>LDY zpg,X</td><td>LDA zpg,X</td><td>LDX zpg,Y</td><td class="undef">---</td><td>CLV impl</td><td>LDA abs,Y</td><td>TSX impl</td><td class="undef">---</td><td>LDY abs,X</td><td>LDA abs,X</td><td>LDX abs,Y</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">C‐</th><td>CPY #</td><td>CMP X,ind</td><td class="undef">---</td><td class="undef">---</td><td>CPY zpg</td><td>CMP zpg</td><td>DEC zpg</td><td class="undef">---</td><td>INY impl</td><td>CMP #</td><td>DEX impl</td><td class="undef">---</td><td>CPY abs</td><td>CMP abs</td><td>DEC abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">D‐</th><td>BNE rel</td><td>CMP ind,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>CMP zpg,X</td><td>DEC zpg,X</td><td class="undef">---</td><td>CLD impl</td><td>CMP abs,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>CMP abs,X</td><td>DEC abs,X</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">E‐</th><td>CPX #</td><td>SBC X,ind</td><td class="undef">---</td><td class="undef">---</td><td>CPX zpg</td><td>SBC zpg</td><td>INC zpg</td><td class="undef">---</td><td>INX impl</td><td>SBC #</td><td>NOP impl</td><td class="undef">---</td><td>CPX abs</td><td>SBC abs</td><td>INC abs</td><td class="undef">---</td>
|
|
</tr>
|
|
<tr>
|
|
<th scope="row">F‐</th><td>BEQ rel</td><td>SBC ind,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>SBC zpg,X</td><td>INC zpg,X</td><td class="undef">---</td><td>SED impl</td><td>SBC abs,Y</td><td class="undef">---</td><td class="undef">---</td><td class="undef">---</td><td>SBC abs,X</td><td>INC abs,X</td><td class="undef">---</td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<p style="margin: 1.5em 0 -1.5em 0;"><input type="checkbox" id="cbxShowIllegals" aria-labeledby="labelCbxShowIllegals" /> <label id="labelCbxShowIllegals" for="cbxShowIllegals">show illegal opcodes</label></p>
|
|
|
|
<h2 class="narrow-margin" id="description">Description</h2>
|
|
<h3>Address Modes</h3>
|
|
<table id="addressmodes" aria-label="table of address modes: (1) abbreviated notation, (2) verbous, (3) formal example, (4) semantical annotations">
|
|
<colgroup>
|
|
<col class="mode"/>
|
|
<col class="mode-verbous"/>
|
|
<col class="notation"/>
|
|
<col class="semantics"/>
|
|
</colgroup>
|
|
<tbody>
|
|
<tr><th scope="row">A</th><td>Accumulator</td><td>OPC A</td><td class="semantics">operand is AC (implied single byte instruction)</td></tr>
|
|
<tr><th scope="row">abs</th><td>absolute</td><td>OPC $LLHH</td><td class="semantics">operand is address $HHLL <a href="#addr-footnote1" class="footnote">*</a></td></tr>
|
|
<tr><th scope="row">abs,X</th><td>absolute, X-indexed</td><td>OPC $LLHH,X</td><td class="semantics">operand is address; effective address is address incremented by X with carry <a href="#addr-footnote2" class="footnote">**</a></td></tr>
|
|
<tr><th scope="row">abs,Y</th><td>absolute, Y-indexed</td><td>OPC $LLHH,Y</td><td class="semantics">operand is address; effective address is address incremented by Y with carry <a href="#addr-footnote2" class="footnote">**</a></td></tr>
|
|
<tr><th scope="row">#</th><td>immediate</td><td>OPC #$BB</td><td class="semantics">operand is byte BB</td></tr>
|
|
<tr><th scope="row">impl</th><td>implied</td><td>OPC</td><td class="semantics">operand implied</td></tr>
|
|
<tr><th scope="row">ind</th><td>indirect</td><td>OPC ($LLHH)</td><td class="semantics">operand is address; effective address is contents of word at address: C.w($HHLL)</td></tr>
|
|
<tr><th scope="row">X,ind</th><td>X-indexed, indirect</td><td>OPC ($LL,X)</td><td class="semantics">operand is zeropage address; effective address is word in (LL + X, LL + X + 1), inc. without carry: C.w($00LL + X)</td></tr>
|
|
<tr><th scope="row">ind,Y</th><td>indirect, Y-indexed</td><td>OPC ($LL),Y</td><td class="semantics">operand is zeropage address; effective address is word in (LL, LL + 1) incremented by Y with carry: C.w($00LL) + Y</td></tr>
|
|
<tr><th scope="row">rel</th><td>relative</td><td>OPC $BB</td><td class="semantics">branch target is PC + signed offset BB <a href="#addr-footnote3" class="footnote">***</a></td></tr>
|
|
<tr><th scope="row">zpg</th><td>zeropage</td><td>OPC $LL</td><td class="semantics">operand is zeropage address (hi-byte is zero, address = $00LL)</td></tr>
|
|
<tr><th scope="row">zpg,X</th><td>zeropage, X-indexed</td><td>OPC $LL,X</td><td class="semantics">operand is zeropage address; effective address is address incremented by X without carry <a href="#addr-footnote2" class="footnote">**</a></td></tr>
|
|
<tr><th scope="row">zpg,Y</th><td>zeropage, Y-indexed</td><td>OPC $LL,Y</td><td class="semantics">operand is zeropage address; effective address is address incremented by Y without carry <a href="#addr-footnote2" class="footnote">**</a></td></tr>
|
|
</tbody>
|
|
</table>
|
|
|
|
<dl class="footnotes" aria-label="footnotes regarding opcode cycles">
|
|
<dt id="addr-footnote1" aria-label="note 1">*</dt><dd>16-bit address words are little endian, lo(w)-byte first, followed by the hi(gh)-byte.<br />
|
|
(An assembler will use a human readable, big-endian notation as in $HHLL.)</dd>
|
|
<dt id="addr-footnote2" aria-label="note 2">**</dt><dd>The available 16-bit address space is conceived as consisting of pages of 256 bytes each, with<br />
|
|
address hi-bytes represententing the page index. An increment with carry may affect the hi-byte<br />
|
|
and may thus result in a crossing of page boundaries, adding an extra cycle to the execution.<br />
|
|
Increments without carry do not affect the hi-byte of an address and no page transitions do occur.<br />
|
|
Generally, increments of 16-bit addresses include a carry, increments of zeropage addresses don't.<br />
|
|
Notably this is not related in any way to the state of the carry bit of the accumulator.</dd>
|
|
<dt id="addr-footnote3" aria-label="note 3">***</dt><dd>Branch offsets are signed 8-bit values, -128 ... +127, negative offsets in two's complement.<br />
|
|
Page transitions may occur and add an extra cycle to the exucution.</dd>
|
|
</dl>
|
|
|
|
<h3 id="byname">Instructions by Name</h3>
|
|
<dl id="opclist" class="opclist" aria-label="list of mnemonics and their verbous equivalent">
|
|
<dt><a href="#ADC" title="instruction details for ADC...">ADC</a></dt><dd>add with carry</dd>
|
|
<dt><a href="#AND" title="instruction details for AND...">AND</a></dt><dd>and (with accumulator)</dd>
|
|
<dt><a href="#ASL" title="instruction details for ASL...">ASL</a></dt><dd>arithmetic shift left</dd>
|
|
<dt><a href="#BCC" title="instruction details for BCC...">BCC</a></dt><dd>branch on carry clear</dd>
|
|
<dt><a href="#BCS" title="instruction details for BCS...">BCS</a></dt><dd>branch on carry set</dd>
|
|
<dt><a href="#BEQ" title="instruction details for BEQ...">BEQ</a></dt><dd>branch on equal (zero set)</dd>
|
|
<dt><a href="#BIT" title="instruction details for BIT...">BIT</a></dt><dd>bit test</dd>
|
|
<dt><a href="#BMI" title="instruction details for BMI...">BMI</a></dt><dd>branch on minus (negative set)</dd>
|
|
<dt><a href="#BNE" title="instruction details for BNE...">BNE</a></dt><dd>branch on not equal (zero clear)</dd>
|
|
<dt><a href="#BPL" title="instruction details for BPL...">BPL</a></dt><dd>branch on plus (negative clear)</dd>
|
|
<dt><a href="#BRK" title="instruction details for BRK...">BRK</a></dt><dd>break / interrupt</dd>
|
|
<dt><a href="#BVC" title="instruction details for BVC...">BVC</a></dt><dd>branch on overflow clear</dd>
|
|
<dt><a href="#BVS" title="instruction details for BVS...">BVS</a></dt><dd>branch on overflow set</dd>
|
|
<dt><a href="#CLC" title="instruction details for CLC...">CLC</a></dt><dd>clear carry</dd>
|
|
<dt><a href="#CLD" title="instruction details for CLD...">CLD</a></dt><dd>clear decimal</dd>
|
|
<dt><a href="#CLI" title="instruction details for CLI...">CLI</a></dt><dd>clear interrupt disable</dd>
|
|
<dt><a href="#CLV" title="instruction details for CLV...">CLV</a></dt><dd>clear overflow</dd>
|
|
<dt><a href="#CMP" title="instruction details for CMP...">CMP</a></dt><dd>compare (with accumulator)</dd>
|
|
<dt><a href="#CPX" title="instruction details for CPX...">CPX</a></dt><dd>compare with X</dd>
|
|
<dt><a href="#CPY" title="instruction details for CPY...">CPY</a></dt><dd>compare with Y</dd>
|
|
<dt><a href="#DEC" title="instruction details for DEC...">DEC</a></dt><dd>decrement</dd>
|
|
<dt><a href="#DEX" title="instruction details for DEX...">DEX</a></dt><dd>decrement X</dd>
|
|
<dt><a href="#DEY" title="instruction details for DEY...">DEY</a></dt><dd>decrement Y</dd>
|
|
<dt><a href="#EOR" title="instruction details for EOR...">EOR</a></dt><dd>exclusive or (with accumulator)</dd>
|
|
<dt><a href="#INC" title="instruction details for INC...">INC</a></dt><dd>increment</dd>
|
|
<dt><a href="#INX" title="instruction details for INX...">INX</a></dt><dd>increment X</dd>
|
|
<dt><a href="#INY" title="instruction details for INY...">INY</a></dt><dd>increment Y</dd>
|
|
<dt><a href="#JMP" title="instruction details for JMP...">JMP</a></dt><dd>jump</dd>
|
|
<dt><a href="#JSR" title="instruction details for JSR...">JSR</a></dt><dd>jump subroutine</dd>
|
|
<dt><a href="#LDA" title="instruction details for LDA...">LDA</a></dt><dd>load accumulator</dd>
|
|
<dt><a href="#LDX" title="instruction details for LDX...">LDX</a></dt><dd>load X</dd>
|
|
<dt><a href="#LDY" title="instruction details for LDY...">LDY</a></dt><dd>load Y</dd>
|
|
<dt><a href="#LSR" title="instruction details for LSR...">LSR</a></dt><dd>logical shift right</dd>
|
|
<dt><a href="#NOP" title="instruction details for NOP...">NOP</a></dt><dd>no operation</dd>
|
|
<dt><a href="#ORA" title="instruction details for ORA...">ORA</a></dt><dd>or with accumulator</dd>
|
|
<dt><a href="#PHA" title="instruction details for PHA...">PHA</a></dt><dd>push accumulator</dd>
|
|
<dt><a href="#PHP" title="instruction details for PHP...">PHP</a></dt><dd>push processor status (SR)</dd>
|
|
<dt><a href="#PLA" title="instruction details for PLA...">PLA</a></dt><dd>pull accumulator</dd>
|
|
<dt><a href="#PLP" title="instruction details for PLP...">PLP</a></dt><dd>pull processor status (SR)</dd>
|
|
<dt><a href="#ROL" title="instruction details for ROL...">ROL</a></dt><dd>rotate left</dd>
|
|
<dt><a href="#ROR" title="instruction details for ROR...">ROR</a></dt><dd>rotate right</dd>
|
|
<dt><a href="#RTI" title="instruction details for RTI...">RTI</a></dt><dd>return from interrupt</dd>
|
|
<dt><a href="#RTS" title="instruction details for RTS...">RTS</a></dt><dd>return from subroutine</dd>
|
|
<dt><a href="#SBC" title="instruction details for SBC...">SBC</a></dt><dd>subtract with carry</dd>
|
|
<dt><a href="#SEC" title="instruction details for SEC...">SEC</a></dt><dd>set carry</dd>
|
|
<dt><a href="#SED" title="instruction details for SED...">SED</a></dt><dd>set decimal</dd>
|
|
<dt><a href="#SEI" title="instruction details for SEI...">SEI</a></dt><dd>set interrupt disable</dd>
|
|
<dt><a href="#STA" title="instruction details for STA...">STA</a></dt><dd>store accumulator</dd>
|
|
<dt><a href="#STX" title="instruction details for STX...">STX</a></dt><dd>store X</dd>
|
|
<dt><a href="#STY" title="instruction details for STY...">STY</a></dt><dd>store Y</dd>
|
|
<dt><a href="#TAX" title="instruction details for TAX...">TAX</a></dt><dd>transfer accumulator to X</dd>
|
|
<dt><a href="#TAY" title="instruction details for TAY...">TAY</a></dt><dd>transfer accumulator to Y</dd>
|
|
<dt><a href="#TSX" title="instruction details for TSX...">TSX</a></dt><dd>transfer stack pointer to X</dd>
|
|
<dt><a href="#TXA" title="instruction details for TXA...">TXA</a></dt><dd>transfer X to accumulator</dd>
|
|
<dt><a href="#TXS" title="instruction details for TXS...">TXS</a></dt><dd>transfer X to stack pointer</dd>
|
|
<dt><a href="#TYA" title="instruction details for TYA...">TYA</a></dt><dd>transfer Y to accumulator</dd>
|
|
</dl>
|
|
|
|
<figure style="margin: 3.25em 0 1.25em 0;padding: 0;box-sizing: border-box;width: 525px;max-width: 100%;">
|
|
<img src="assets/mcs6502-block-diagram.svg" width="525" height="658" alt="Block diagram 6502 processor" style="width: 100%;height:auto;" />
|
|
<figcaption style="text-align: center;color:#484848;line-height:120%;margin-top:1.25em;">Block diagram of the NMOS 6502 CPU.<br />After (6501 specifics omitted):<br />MCS6502 Microcomputer Family Hardware Manual; Jannuary 1976.<br />MOS Technology, Inc., Norristown/PA, 1976.</figcaption>
|
|
</figure>
|
|
|
|
<h3 id="registers">Registers</h3>
|
|
<table id="registers" aria-label="table of registers and their verbous names" style="margin-left: 1em;">
|
|
<tr><td>PC</td><td>program counter</td><td align="right">(16 bit)</td></tr>
|
|
<tr><td>AC</td><td>accumulator</td><td align="right">(8 bit)</td></tr>
|
|
<tr><td>X</td><td>X register</td><td align="right">(8 bit)</td></tr>
|
|
<tr><td>Y</td><td>Y register</td><td align="right">(8 bit)</td></tr>
|
|
<tr><td>SR</td><td>status register [NV-BDIZC]</td><td align="right">(8 bit)</td></tr>
|
|
<tr><td>SP</td><td>stack pointer</td><td align="right">(8 bit)</td></tr>
|
|
</table>
|
|
|
|
<p>Note: The status register (SR) is also known as the P register,<br>the accumulator (AC) as just A, the stack pointer (SP) as S, and<br />X and Y registers as XR and YR respectively.</p><p>Machine language monitors show them typically like,</p>
|
|
<pre style="color:#01571D;"> PC IRQ SR AC XR YR SP
|
|
0401 E62E 32 04 5E 00 F8</pre>
|
|
<p>("IRQ" is not a register, but the interrupt request vector, see below.)</P>
|
|
|
|
<ul class="flaglist">
|
|
<li>The <strong>accumulator</strong> is the main rgister of the 6502. Its content is typically used by the arithmetic logic unit (ALU) for the first operand and results are deposited in the accumulator again. Thus its name, as results accumulate in this register. Most arithmetic and logical operations interact with this register.</li>
|
|
<li>The <strong>X</strong> and <strong>Y</strong> registers are auxiliary registers. Like the accumulator, they can be loaded directly with values, both immediatedly (as literal constants) or from memory. Additionally, they can be incremented and decremented, and their contents may be transferred to and from the acuumulator. Their main purpose is the use as index registers, where their contents is added to a base memory location, before any values are either stored to or retrieved from the resulting address, which is known as the <i>effective address</i>. This is commonly used for loops and table lookups at a given index, hence the name. (See <a href="#modes">address modes</a>, below.)</li>
|
|
<li>The <strong>program counter</strong> keeps track of the memory location holding the current instruction code. Its contents is automatically stepped up as the program is executed and is modified by branch and jump operations. As it must be able to address the full 16-bit address range of 64K bytes, it's the only 16-bit register of the 6502.</li>
|
|
<li>The <strong>stack pointer</strong> points to the current <em>top of stack</em> (or rather, to its bottom, as the stack grows top-down.) The <i>processor stack</i> is located on memory page #1 ($0100–$01FF), a 256 bytes <i>last-in-first-out</i> (LIFO) stack, which enables subroutines and also serves as a quick intermediate storage. As a 8-bit register, the stack pointer holds just the low-byte of this address (the offset from $0100.)<br/>Be aware that this will just wrap around, in case that the stack underflows.</li>
|
|
<li>The <strong>status register</strong> holds the status of the processor, consisting of flags reflecting results of previous operations, configuration flags, like disabeling (blocking) interrupts or setting up binary encoded decimal mode (BCD), and the carry flag, which enables multi-byte arithmetics.</li>
|
|
</ul>
|
|
|
|
<h4><strong>Status Register Flags</strong> (bit 7 to bit 0)</h4>
|
|
<table id="flags" aria-label="table of status register flags and their verbous names" style="margin-left: 1em;">
|
|
<td>N</td><td>Negative</td></tr>
|
|
<td>V</td><td>Overflow</td></tr>
|
|
<td>-</td><td>ignored</td></tr>
|
|
<td>B</td><td>Break</td></tr>
|
|
<td>D</td><td>Decimal (use BCD for arithmetics)</td></tr>
|
|
<td>I</td><td>Interrupt (IRQ disable)</td></tr>
|
|
<td>Z</td><td>Zero</td></tr>
|
|
<td>C</td><td>Carry</td></tr>
|
|
</table>
|
|
|
|
<ul class="flaglist">
|
|
<li>The <strong>zero flag</strong> (Z) indicates a value of all zero bits and the <strong>negative flag</strong> (N) indicates the presence of a set sign bit in bit-position 7. These flags are always updated, whenever a value is transferred to a CPU register (A,X,Y) and as a result of any logical ALU operations. The Z and N flags are also updated by increment and decrement operations acting on a memory location.</li>
|
|
<li>The <strong>carry flag</strong> (C) flag is used as a buffer and as a borrow in arithmetic operations. Any comparisons will update this additionally to the Z and N flags, as do shift and rotate operations.</li>
|
|
<li>All arithmetic operations update the Z, N, C and V flags.</li>
|
|
<li>The <strong>overflow flag</strong> (V) indicates overflow with signed
|
|
binary arithmetics. As a signed byte represents a range of -128 to +127, an
|
|
overflow can never occur when the operands are of opposite sign, since the
|
|
result will never exceed this range. Thus, overflow may only occur, if both
|
|
operands are of the same sign. Then, the result must be also of the same sign.
|
|
Otherwise, overflow is detected and the overflow flag is set.
|
|
(I.e., both operands have a zero in the sign position at bit 7, but bit 7 of the
|
|
result is 1, or, both operands have the sign-bit set, but the result is positive.)</li>
|
|
<li>The <strong>decimal flag</strong> (D) sets the ALU to binary coded decimal (BCD) mode for additions and subtractions (ADC, SBC).</li>
|
|
<li>The <strong>interrupt inhibit flag</strong> (I) blocks any maskable interrupt requests (IRQ).</li>
|
|
<li>The <strong>break flag</strong> (B) is not an actual flag implemented in a register, and rather
|
|
appears only, when the status register is pushed onto or pulled from the stack.
|
|
When pushed, it will be 1 when transfered by a BRK or PHP instruction, and
|
|
zero otherwise (i.e., when pushed by a hardware interrupt).
|
|
When pulled into the status register (by PLP or on RTI), it will be ignored.<br />
|
|
In other words, the break flag will be inserted, whenever the status register
|
|
is transferred to the stack by software (BRK or PHP), and will be zero, when
|
|
transferred by hardware. Since there is no actual slot for the break flag, it
|
|
will be always ignored, when retrieved (PLP or RTI).
|
|
The break flag is not accessed by the CPU at anytime and there is no internal
|
|
representation. Its purpose is more for patching, to discern an interrupt caused
|
|
by a BRK instruction from a normal interrupt initiated by hardware.</li>
|
|
<li>Any of these flags (but the break flag) may be set or cleared by dedicated instructions. Moreover, there are branch instructions to conditionally divert the control flow depending on the respective state of the Z, N, C or V flag.</li>
|
|
</ul>
|
|
|
|
<h3>Processor Stack</h3>
|
|
<p>LIFO, top-down, 8 bit range, 0x0100 - 0x01FF</p>
|
|
|
|
<h3>Bytes, Words, Addressing</h3>
|
|
<p>8 bit bytes, 16 bit words in lobyte-hibyte representation (Little-Endian).<br />
|
|
16 bit address range, operands follow instruction codes.</p>
|
|
|
|
<p>Signed values are two's complement, sign in bit 7 (most significant bit).<br />
|
|
(%11111111 = $FF = -1, %10000000 = $80 = -128, %01111111 = $7F = +127)<br />
|
|
Signed binary and binary coded decimal (BCD) arithmetic modes.</p>
|
|
|
|
<h3>System Vectors</h3>
|
|
<p>$FFFA, $FFFB ... NMI (Non-Maskable Interrupt) vector, 16-bit (LB, HB)<br />
|
|
$FFFC, $FFFD ... RES (Reset) vector, 16-bit (LB, HB)<br />
|
|
$FFFE, $FFFF ... IRQ (Interrupt Request) vector, 16-bit (LB, HB)</p>
|
|
|
|
<h4>Start/Reset Operations</h4>
|
|
<p>An active-low reset line allows to hold the processor in a known disabled<br />
|
|
state, while the system is initialized. As the reset line goes high, the<br />
|
|
processor performs a start sequence of 7 cycles, at the end of which the<br />
|
|
program counter (PC) is read from the address provided in the 16-bit reset<br />
|
|
vector at $FFFC (LB-HB). Then, at the eighth cycle, the processor transfers<br />
|
|
control by performing a JMP to the provided address.<br />
|
|
Any other initializations are left to the thus executed program. (Notably,<br />
|
|
instructions exist for the initialization and loading of all registers, but<br />
|
|
for the program counter, which is provided by the reset vector at $FFFC.)</p>
|
|
|
|
|
|
<h3 id="bytype">Instructions by Type</h3>
|
|
<ul class="bytypelist">
|
|
<li><h4>Transfer Instructions</h4>
|
|
<p>Load, store, interregister transfer</p>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#LDA" title="instruction details for LDA...">LDA</a></dt><dd>load accumulator</dd>
|
|
<dt><a href="#LDX" title="instruction details for LDX...">LDX</a></dt><dd>load X</dd>
|
|
<dt><a href="#LDY" title="instruction details for LDY...">LDY</a></dt><dd>load Y</dd>
|
|
<dt><a href="#STA" title="instruction details for STA...">STA</a></dt><dd>store accumulator</dd>
|
|
<dt><a href="#STX" title="instruction details for STX...">STX</a></dt><dd>store X</dd>
|
|
<dt><a href="#STY" title="instruction details for STY...">STY</a></dt><dd>store Y</dd>
|
|
<dt><a href="#TAX" title="instruction details for TAX...">TAX</a></dt><dd>transfer accumulator to X</dd>
|
|
<dt><a href="#TAY" title="instruction details for TAY...">TAY</a></dt><dd>transfer accumulator to Y</dd>
|
|
<dt><a href="#TSX" title="instruction details for TSX...">TSX</a></dt><dd>transfer stack pointer to X</dd>
|
|
<dt><a href="#TXA" title="instruction details for TXA...">TXA</a></dt><dd>transfer X to accumulator</dd>
|
|
<dt><a href="#TXS" title="instruction details for TXS...">TXS</a></dt><dd>transfer X to stack pointer</dd>
|
|
<dt><a href="#TYA" title="instruction details for TYA...">TYA</a></dt><dd>transfer Y to accumulator</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Stack Instructions</h4>
|
|
<p>These instructions transfer the accumulator or status register (flags) to and from the stack. The processor stack is a last-in-first-out (LIFO) stack of 256 bytes length, implemented at addresses $0100 - $01FF. The stack grows down as new values are pushed onto it with the current insertion point maintained in the stack pointer register.<br />(When a byte is pushed onto the stack, it will be stored in the address indicated by the value currently in the stack pointer, which will be then decremented by 1. Conversely, when a value is pulled from the stack, the stack pointer is incremented. The stack pointer is accessible by the <a href="#TSX" title="instruction details for TSX...">TSX</a> and <a href="#TXS" title="instruction details for TXS...">TXS</a> instructions.)</p>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#PHA" title="instruction details for PHA...">PHA</a></dt><dd>push accumulator</dd>
|
|
<dt><a href="#PHP" title="instruction details for PHP...">PHP</a></dt><dd>push processor status register (with break flag set)</dd>
|
|
<dt><a href="#PLA" title="instruction details for PLA...">PLA</a></dt><dd>pull accumulator</dd>
|
|
<dt><a href="#PLP" title="instruction details for PLP...">PLP</a></dt><dd>pull processor status register</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Decrements & Increments</h4>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#DEC" title="instruction details for DEC...">DEC</a></dt><dd>decrement (memory)</dd>
|
|
<dt><a href="#DEX" title="instruction details for DEX...">DEX</a></dt><dd>decrement X</dd>
|
|
<dt><a href="#DEY" title="instruction details for DEY...">DEY</a></dt><dd>decrement Y</dd>
|
|
<dt><a href="#INC" title="instruction details for INC...">INC</a></dt><dd>increment (memory)</dd>
|
|
<dt><a href="#INX" title="instruction details for INX...">INX</a></dt><dd>increment X</dd>
|
|
<dt><a href="#INY" title="instruction details for INY...">INY</a></dt><dd>increment Y</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Arithmetic Operations</h4>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#ADC" title="instruction details for ADC...">ADC</a></dt><dd>add with carry (prepare by <a href="#CLC" title="instruction details for CLC...">CLC</a>)</dd>
|
|
<dt><a href="#SBC" title="instruction details for SBC...">SBC</a></dt><dd>subtract with carry (prepare by <a href="#SEC" title="instruction details for SEC...">SEC</a>)</dd>
|
|
</dl>
|
|
<p>See the <a href="#arithmetic">Primer of 6502 Arithmetic Instructions</a> below for details.</p>
|
|
</li>
|
|
<li><h4>Logical Operations</h4>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#AND" title="instruction details for AND...">AND</a></dt><dd>and (with accumulator)</dd>
|
|
<dt><a href="#EOR" title="instruction details for EOR...">EOR</a></dt><dd>exclusive or (with accumulator)</dd>
|
|
<dt><a href="#ORA" title="instruction details for ORA...">ORA</a></dt><dd>(inclusive) or with accumulator</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Shift & Rotate Instructions</h4>
|
|
<p>All shift and rotate instructions preserve the bit shifted out in the carry flag.</p>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#ASL" title="instruction details for ASL...">ASL</a></dt><dd>arithmetic shift left (shifts in a zero bit on the right)</dd>
|
|
<dt><a href="#LSR" title="instruction details for LSR...">LSR</a></dt><dd>logical shift right (shifts in a zero bit on the left)</dd>
|
|
<dt><a href="#ROL" title="instruction details for ROL...">ROL</a></dt><dd>rotate left (shifts in carry bit on the right)</dd>
|
|
<dt><a href="#ROR" title="instruction details for ROR...">ROR</a></dt><dd>rotate right (shifts in zero bit on the left)</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Flag Instructions</h4>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#CLC" title="instruction details for CLC...">CLC</a></dt><dd>clear carry</dd>
|
|
<dt><a href="#CLD" title="instruction details for CLD...">CLD</a></dt><dd>clear decimal (BCD arithmetics disabled)</dd>
|
|
<dt><a href="#CLI" title="instruction details for CLI...">CLI</a></dt><dd>clear interrupt disable</dd>
|
|
<dt><a href="#CLV" title="instruction details for CLV...">CLV</a></dt><dd>clear overflow</dd>
|
|
<dt><a href="#SEC" title="instruction details for SEC...">SEC</a></dt><dd>set carry</dd>
|
|
<dt><a href="#SED" title="instruction details for SED...">SED</a></dt><dd>set decimal (BCD arithmetics enabled)</dd>
|
|
<dt><a href="#SEI" title="instruction details for SEI...">SEI</a></dt><dd>set interrupt disable</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Comparisons</h4>
|
|
<p>Generally, comparison instructions subtract the operand from the given register without affecting this register. Flags are still set as with a normal subtraction and thus the relation of the two values becomes accessible by the Zero, Carry and Negative flags.<br />(See the branch instructions below for how to evaluate flags.)</p>
|
|
<table class="comparison">
|
|
<tr><td><em>Relation R − Op</em></td><td>Z</td><td>C</td><td>N</td></tr>
|
|
<tr><td>Register < Operand</td><td>0</td><td>0</td><td><em>sign bit of result</em></td></tr>
|
|
<tr><td>Register = Operand</td><td>1</td><td>1</td><td>0</td></tr>
|
|
<tr><td>Register > Operand</td><td>0</td><td>1</td><td><em>sign bit of result</em></td></tr>
|
|
</table>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#CMP" title="instruction details for CMP...">CMP</a></dt><dd>compare (with accumulator)</dd>
|
|
<dt><a href="#CPX" title="instruction details for CPX...">CPX</a></dt><dd>compare with X</dd>
|
|
<dt><a href="#CPY" title="instruction details for CPY...">CPY</a></dt><dd>compare with Y</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Conditional Branch Instructions</h4>
|
|
<p>Branch targets are relative, signed 8-bit address offsets. (An offset of #0 corresponds to the immedately following address — or a rather odd and expensive NOP.)</p>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#BCC" title="instruction details for BCC...">BCC</a></dt><dd>branch on carry clear</dd>
|
|
<dt><a href="#BCS" title="instruction details for BCS...">BCS</a></dt><dd>branch on carry set</dd>
|
|
<dt><a href="#BEQ" title="instruction details for BEQ...">BEQ</a></dt><dd>branch on equal (zero set)</dd>
|
|
<dt><a href="#BMI" title="instruction details for BMI...">BMI</a></dt><dd>branch on minus (negative set)</dd>
|
|
<dt><a href="#BNE" title="instruction details for BNE...">BNE</a></dt><dd>branch on not equal (zero clear)</dd>
|
|
<dt><a href="#BPL" title="instruction details for BPL...">BPL</a></dt><dd>branch on plus (negative clear)</dd>
|
|
<dt><a href="#BVC" title="instruction details for BVC...">BVC</a></dt><dd>branch on overflow clear</dd>
|
|
<dt><a href="#BVS" title="instruction details for BVS...">BVS</a></dt><dd>branch on overflow set</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Jumps & Subroutines</h4>
|
|
<p>JSR and RTS affect the stack as the return address is pushed onto or pulled from the stack, respectively.<br />(JSR will first push the high-byte of the return address [PC+2] onto the stack, then the low-byte. The stack will then contain, seen from the bottom or from the most recently added byte, [PC+2]-L [PC+2]-H.)</p>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#JMP" title="instruction details for JMP...">JMP</a></dt><dd>jump</dd>
|
|
<dt><a href="#JSR" title="instruction details for JSR...">JSR</a></dt><dd>jump subroutine</dd>
|
|
<dt><a href="#RTS" title="instruction details for RTS...">RTS</a></dt><dd>return from subroutine</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Interrupts</h4>
|
|
<p>A hardware interrupt (maskable IRQ and non-maskable NMI), will cause the processor to put first the address currently in the program counter onto the stack (in HB-LB order), followed by the value of the status register. (The stack will now contain, seen from the bottom or from the most recently added byte, SR PC-L PC-H with the stack pointer pointing to the address below the stored contents of status register.) Then, the processor will divert its control flow to the address provided in the two word-size interrupt vectors at $FFFA (IRQ) and $FFFE (NMI).<br />
|
|
A set interrupt disable flag will inhibit the execution of an IRQ, but not of a NMI, which will be executed anyways.<br />
|
|
The break instruction (BRK) behaves like a NMI, but will push the value of PC+2 onto the stack to be used as the return address. Also, as with any software initiated transfer of the status register to the stack, the break flag will be found set on the respective value pushed onto the stack. Then, control is transferred to the address in the NMI-vector at $FFFE.<br />
|
|
In any way, the interrupt disable flag is set to inhibit any further IRQ as control is transferred to the interrupt handler specified by the respective interrupt vector.</p>
|
|
<p>The RTI instruction restores the status register from the stack and behaves otherwise like the JSR instruction. (The break flag is always ignored as the status is read from the stack, as it isn't a real processor flag anyway.)</p>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#BRK" title="instruction details for BRK...">BRK</a></dt><dd>break / software interrupt</dd>
|
|
<dt><a href="#RTI" title="instruction details for RTI...">RTI</a></dt><dd>return from interrupt</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Other</h4>
|
|
<dl class="opclist" aria-label="mnemonics and verbous equivalents">
|
|
<dt><a href="#BIT" title="instruction details for BIT...">BIT</a></dt><dd>bit test (accumulator & memory)</dd>
|
|
<dt><a href="#NOP" title="instruction details for NOP...">NOP</a></dt><dd>no operation</dd>
|
|
</dl>
|
|
</li>
|
|
</ul>
|
|
|
|
<h3 id="modes">6502 Address Modes in Detail</h3>
|
|
<p style="width: 450px; max-width: 100%; white-space: normal;">(This section, especially the diagrams included, is heavily inspired by the Acorn Atom manual "<a href="https://archive.org/details/atomic_theory_and_practice" target="_blank" rel="noopener">Atomic Theory and Practice</a>" by David Johnson Davies, Acorn Computers Limited, 2<sup>nd</sup> ed. 1980, p 118–121.)
|
|
<ul class="bytypelist">
|
|
<li><h4>Implied Addressing</h4>
|
|
<p>These instructions act directly on one or more registers or flags internal to the CPU. Therefor, these instructions are principally single-byte instructions, lacking an explicit operand. The operand is implied, as it is already provided by the very instruction.</p>
|
|
<p>Instructions targeting exclusively the contents of the accumulator may or may not be denoted by using an explicit "A" as the operand, depending on the flavor of syntax. (This may be regarded as a special address mode of its own, but it is really a special case of an implied instruction. It is still a single-byte instruction and no operand is provided in machine language.)</p>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist wide" aria-label="examples: mnemonic and meaning">
|
|
<dt>CLC</dt><dd>clear the carry flag</dd>
|
|
<dt>ROL A</dt><dd>rotate contents of accumulator left by one position</dd>
|
|
<dt>ROL</dt><dd>same as above, implicit notation (A implied)</dd>
|
|
<dt>TXA</dt><dd>transfer contents of X-register to the accumulator</dd>
|
|
<dt>PHA</dt><dd>push the contents of the accumulator to the stack</dd>
|
|
<dt>RTS</dt><dd>return from subroutine (by pulling PC from stack)</dd>
|
|
</dl>
|
|
<p>Mind that some of these instructions, while simple in appearance, may be quite complex operations, like "PHA", which involves the accumulator, the stack pointer and memory access.</p></li>
|
|
<li><h4>Immediate Addressing</h4>
|
|
<p>Here, a literal operand is given immediately after the instruction. The operand is always an 8-bit value and the total instruction length is always 2 bytes. In memory, the operand is a single byte following immediately after the instruction code. In assembler, the mode is usually indicated by a "#" prefix adjacent to the operand.</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="300px" height="90px" viewBox="0 0 300 90" role="img" aria-label="Illustration of addressing mode">
|
|
<defs>
|
|
<style>
|
|
g.addrxmp text
|
|
{
|
|
font-size: 11px;
|
|
font-family: 'm-1m',courier,monospace;
|
|
font-style: normal;
|
|
font-weight: 400;
|
|
line-height: normal;
|
|
text-align: left;
|
|
fill: #000;
|
|
letter-spacing: 0.04em;
|
|
text-shadow: none;
|
|
}
|
|
g.addrxmp text.caption { letter-spacing: 0.01em; }
|
|
g.addrxmp rect { stroke: #32869e; stroke-width: 1; fill: none; }
|
|
g.addrxmp line.indexed { stroke: #000; stroke-width: 1; }
|
|
g.addrxmp line.result { stroke: #32869edd; stroke-width: 4; marker-end: url('#addrxmp-arrowhead'); }
|
|
</style>
|
|
<marker id="addrxmp-arrowhead" viewBox="0 0 7 7" refX="0" refY="3.5"
|
|
markerWidth="3" markerHeight="3" fill="#32869edd"
|
|
orient="auto-start-reverse">
|
|
<path d="M 0 0 L 4.5 3.5 L 0 7 z" />
|
|
</marker>
|
|
</defs>
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="80" y="10">Instruction</text>
|
|
<text x="2" y="35">LDA #7</text><text x="95" y="35">A9</text><text x="115" y="35">07</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<text x="93" y="80">A:</text><text x="115" y="80">07</text>
|
|
<rect x="110.5" y="66.5" width="20" height="19" />
|
|
<line x1="120" x2="120" y1="45" y2="55" class="result" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist wide" aria-label="examples: mnemonic and meaning">
|
|
<dt>LDA #$07</dt><dd>load the literal hexidecimal value "$7" into the accumulator</dd>
|
|
<dt>ADC #$A0</dt><dd>add the literal hexidecimal value "$A0" to the accumulator</dd>
|
|
<dt>CPX #$32</dt><dd>compare the X-register to the literal hexidecimal value "$32"</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Absolute Addressing</h4>
|
|
<p>Absolute addressing modes provides the 16-bit address of a memory location, the contents of which used as the operand to the instruction. In machine language, the address is provided in two bytes immediately after the instruction (making these 3-byte instructions) in low-byte, high-byte order (LLHH) or little-endian. In assembler, conventional numbers (HHLL order or big-endian words) are used to provide the address.</p>
|
|
<p>Absolute addresses are also used for the jump instructions JMP and JSR to provide the address for the next instruction to continue with in the control flow.</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="300px" height="90px" viewBox="0 0 300 90" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="90" y="10">Instruction</text><text class="caption" x="214" y="10">Data</text>
|
|
<text x="2" y="35">LDA $3010</text><text x="95" y="35">AD</text><text x="115" y="35">10</text><text x="135" y="35">30</text><text x="175" y="35">$3010:</text><text x="220" y="35">34</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<rect x="130.5" y="21.5" width="20" height="19" />
|
|
<rect x="215.5" y="21.5" width="20" height="19" />
|
|
<text x="198" y="80">A:</text><text x="220" y="80">34</text>
|
|
<rect x="215.5" y="66.5" width="20" height="19" />
|
|
<line x1="225" x2="225" y1="45" y2="55" class="result" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist wide" aria-label="examples: mnemonic and meaning">
|
|
<dt>LDA $3010</dt><dd>load the contents of address "$3010" into the accumulator</dd>
|
|
<dt>ROL $08A0</dt><dd>rotate the contents of address "$08A0" left by one position</dd>
|
|
<dt>JMP $4000</dt><dd>jump to (continue with) location "$4000"</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Zero-Page Addressing</h4>
|
|
<p>The 16-bit address space available to the 6502 is thought to consist of 256 "pages" of 256 memory locations each ($00…$FF). In this model the high-byte of an address gives the page number and the low-byte a location inside this page. The very first of these pages, where the high-byte is zero (addresses $0000…$00FF), is somewhat special.</p>
|
|
<p>The zero-page address mode is similar to absolute address mode, but these instructions use only a single byte for the operand, the low-byte, while the high-byte is assumed to be zero by definition. Therefore, these instructions have a total length of just two bytes (one less than absolute mode) and take one CPU cycle less to execute, as there is one byte less to fetch.</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="300px" height="90px" viewBox="0 0 300 90" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="80" y="10">Instruction</text><text class="caption" x="214" y="10">Data</text>
|
|
<text x="2" y="35">LDA $80</text><text x="95" y="35">A5</text><text x="115" y="35">80</text><text x="175" y="35">$0080:</text><text x="220" y="35">34</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<rect x="215.5" y="21.5" width="20" height="19" />
|
|
<text x="198" y="80">A:</text><text x="220" y="80">34</text>
|
|
<rect x="215.5" y="66.5" width="20" height="19" />
|
|
<line x1="225" x2="225" y1="45" y2="55" class="result" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist wide" aria-label="examples: mnemonic and meaning">
|
|
<dt>LDA $80</dt><dd>load the contents of address "$0080" into the accumulator</dd>
|
|
<dt>BIT $A2</dt><dd>perform bit-test with the contents of address "$00A2"</dd>
|
|
<dt>ASL $9A</dt><dd>arithmetic shift left of the contents of location "$009A"</dd>
|
|
</dl>
|
|
<p>(One way to think of the zero-page is as a page of 256 additional registers, somewhat slower than the internal registers, but with zero-page instructions also faster executing than "normal" instructions. The zero-page has a few more tricks up its sleeve, making these addresses perform more like real registers, see below.)</p>
|
|
</li>
|
|
<li><h4>Indexed Addressing: Absolute,X and Absolute,Y</h4>
|
|
<p>Indexed addressing adds the contents of either the X-register or the Y-register to the provided address to give the <em>effective address</em>, which provides the operand.</p>
|
|
<p>These instructions are usefull to e.g., load values from tables or to write to a continuous segment of memory in a loop. The most basic forms are "absolute,X" and "absolute,X", where either the X- or the Y-register, respectively, is added to a given base address. As the base address is a 16-bit value, these are generally 3-byte instructions. Since there is an additional operation to perform to determine the effective address, these instructions are one cycle slower than those using absolute addressing mode.*</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="300px" height="120px" viewBox="0 0 300 120" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="90" y="10">Instruction</text><text class="caption" x="224" y="10">Data</text>
|
|
<text x="2" y="35">LDA $3120,X</text><text x="95" y="35">BD</text><text x="115" y="35">20</text><text x="135" y="35">31</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<rect x="130.5" y="21.5" width="20" height="19" />
|
|
<text x="160" y="60">+ =</text><text x="185" y="60">$3132:</text><text x="230" y="60">78</text>
|
|
<rect x="225.5" y="46.5" width="20" height="19" />
|
|
<text x="112" y="85">X:</text><text x="135" y="85">12</text>
|
|
<rect x="130.5" y="71.5" width="20" height="19" />
|
|
<line x1="151" x2="159.5" y1="42" y2="53" class="indexed" />
|
|
<line x1="151" x2="159.5" y1="70" y2="59" class="indexed" />
|
|
<text x="208" y="110">A:</text><text x="230" y="110">78</text>
|
|
<rect x="225.5" y="96.5" width="20" height="19" />
|
|
<line x1="235" x2="235" y1="70" y2="85" class="result" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist xwide" aria-label="examples: mnemonic and meaning">
|
|
<dt>LDA $3120,X</dt><dd>load the contents of address "$3120 + X" into A</dd>
|
|
<dt>LDX $8240,Y</dt><dd>load the contents of address "$8240 + Y" into X</dd>
|
|
<dt>INC $1400,X</dt><dd>increment the contents of address "$1400 + X"</dd>
|
|
</dl>
|
|
<p>*) If the addition of the contents of the index register effects in a change of the high-byte given by the base address so that the effective address is on the next memory page, the additional operation to increment the high-byte takes another CPU cycle. This is also known as a crossing of page boundaries.</p>
|
|
</li>
|
|
<li><h4>Indexed Addressing: Zero-Page,X (and Zero-Page,Y)</h4>
|
|
<p>As with absolute addressing, there is also a zero-page mode for indexed addressing. However, this is generally only available with the X-register. (The only exception to this is LDX, which has an indexed zero-page mode utilizing the Y-register.)<br />As we have already seen with normal zero-page mode, these instructions are one byte less in total length (two bytes) and take one CPU cycle less than instructions in absolute indexed mode.</p>
|
|
<p>Unlike absolute indexed instructions with 16-bit base addresses, zero-page indexed instructions never affect the high-byte of the effective address, which will simply wrap around in the zero-page, and there is no penalty for crossing any page boundaries.</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="300px" height="120px" viewBox="0 0 300 120" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="80" y="10">Instruction</text><text class="caption" x="204" y="10">Data</text>
|
|
<text x="2" y="35">LDA $80,X</text><text x="95" y="35">B6</text><text x="115" y="35">80</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<text x="140" y="60">+ =</text><text x="165" y="60">$0082:</text><text x="210" y="60">64</text>
|
|
<rect x="205.5" y="46.5" width="20" height="19" />
|
|
<text x="92" y="85">X:</text><text x="115" y="85">02</text>
|
|
<rect x="110.5" y="71.5" width="20" height="19" />
|
|
<line x1="131" x2="139.5" y1="42" y2="52.5" class="indexed" />
|
|
<line x1="131" x2="139.5" y1="70" y2="59.5" class="indexed" />
|
|
<text x="188" y="110">A:</text><text x="210" y="110">64</text>
|
|
<rect x="205.5" y="96.5" width="20" height="19" />
|
|
<line x1="215" x2="215" y1="70" y2="85" class="result" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist wide" aria-label="examples: mnemonic and meaning">
|
|
<dt>LDA $80,X</dt><dd>load the contents of address "$0080 + X" into A</dd>
|
|
<dt>LSR $82,X</dt><dd>shift the contents of address "$0082 + X" left</dd>
|
|
<dt>LDX $60,Y</dt><dd>load the contents of address "$0060 + Y" into X</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Indirect Addressing</h4>
|
|
<p>This mode looks up a given address and uses the contents of this address and the next one (in LLHH little-endian order) as the effective address. In its basic form, this mode is available for the JMP instruction only. (Its generally use is jump vectors and jump tables.)<br />Like the absolute JMP instruction it uses a 16-bit address (3 bytes in total), but takes two additional CPU cycles to execute, since there are two additional bytes to fetch for the lookup of the effective jump target.</p>
|
|
<p>Generally, indirect addressing is denoted by putting the lookup address in parenthesis.</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="370px" height="90px" viewBox="0 0 370 90" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="90" y="10">Instruction</text><text class="caption" x="218" y="10">Lookup</text>
|
|
<text x="2" y="35">JMP ($FF82)</text><text x="95" y="35">6C</text><text x="115" y="35">82</text><text x="135" y="35">FF</text>
|
|
<text x="175" y="35">$FF82:</text><text x="220" y="35">C4</text><text x="240" y="35">80</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<rect x="130.5" y="21.5" width="20" height="19" />
|
|
<rect x="215.5" y="21.5" width="20" height="19" />
|
|
<rect x="235.5" y="21.5" width="20" height="19" />
|
|
<text x="190" y="80">PC:</text><text x="220" y="80">$80C4</text><text x="265" y="80" class="caption">(Effective Target)</text>
|
|
<line x1="235" x2="235" y1="45" y2="58" class="result" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Example:</p>
|
|
<dl class="opclist xwide" aria-label="examples: mnemonic and meaning">
|
|
<dt>JMP ($FF82)</dt><dd>jump to address given in addresses "$FF82" and "$FF83"</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Pre-Indexed Indirect, "(Zero-Page,X)"</h4>
|
|
<p>Indexed indirect address modes are generally available only for instructions supplying an operand to the accumulator (LDA, STA, ADC, SBC, AND, ORA, EOR, etc). The placement of the index register inside or outside of the parenthesis indicating the address lookup will give you clue what these instructions are doing.</p>
|
|
<p>Pre-indexed indirect address mode is only available in combination with the X-register. It works much like the "zero-page,X" mode, but, after the X-register has been added to the base address, instead of directly accessing this, an additional lookup is performed, reading the contents of resulting address and the next one (in LLHH little-endian order), in order to determine the effective address.</p>
|
|
<p>Like with "zero-page,X" mode, the total instruction length is 2 bytes, but there are two additional CPU cycles in order to fetch the effective 16-bit address. As "zero-page,X" mode, a lookup address will never overflow into the next page, but will simply wrap around in the zero-page.</p>
|
|
<p>These instructions are useful, whenever we want to loop over a table of pointers to disperse addresses, or where we want to apply the same operation to various addresses, which we have stored as a table in the zero-page.</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="335px" height="120px" viewBox="0 0 335 120" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="80" y="10">Instruction</text><text class="caption" x="208" y="10">Lookup</text><text class="caption" x="309" y="10">Data</text>
|
|
<text x="2" y="35">LDA ($70,X)</text><text x="95" y="35">A1</text><text x="115" y="35">70</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<text x="140" y="60">+ =</text><text x="165" y="60">$0075:</text><text x="210" y="60">23</text><text x="230" y="60">30</text>
|
|
<rect x="205.5" y="46.5" width="20" height="19" />
|
|
<rect x="225.5" y="46.5" width="20" height="19" />
|
|
<text x="270" y="60">$3023:</text><text x="315" y="60">A5</text>
|
|
<rect x="310.5" y="46.5" width="20" height="19" />
|
|
<text x="92" y="85">X:</text><text x="115" y="85">05</text>
|
|
<rect x="110.5" y="71.5" width="20" height="19" />
|
|
<line x1="131" x2="139.5" y1="42" y2="52.5" class="indexed" />
|
|
<line x1="131" x2="139.5" y1="70" y2="59.5" class="indexed" />
|
|
<text x="293" y="110">A:</text><text x="315" y="110">A5</text>
|
|
<rect x="310.5" y="96.5" width="20" height="19" />
|
|
<line x1="320" x2="320" y1="70" y2="85" class="result" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist xwide" aria-label="examples: mnemonic and meaning">
|
|
<dt>LDA ($70,X)</dt><dd>load the contents of the location given in addresses<br />"$0070+X" and "$0070+1+X" into A</dd>
|
|
<dt>STA ($A2,X)</dt><dd>store the contents of A in the location given in<br />addresses "$00A2+X" and "$00A3+X"</dd>
|
|
<dt>EOR ($BA,X)</dt><dd>perform an exlusive OR of the contents of A and the contents<br />of the location given in addresses "$00BA+X" and "$00BB+X"</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Post-Indexed Indirect, "(Zero-Page),Y"</h4>
|
|
<p>Post-indexed indirect addressing is only available in combination with the Y-register. As indicated by the indexing term ",Y" being appended to the outside of the parenthesis indicating the indirect lookup, here, a pointer is first read (from the given zero-page address) and resolved and only then the contents of the Y-register is added to this to give the effective address.</p>
|
|
<p>Like with "zero-page,Y" mode, the total instruction length is 2 bytes, but there it takes an additional CPU cycles to resolve and index the 16-bit pointer. As with "absolute,X" mode, the effective address may overflow into the next page, in the case of which the execution uses an extra CPU cycle.</p>
|
|
<p>These instructions are useful, wherever we want to perform lookups on varying bases addresses or whenever we want to loop over tables, the base address of which we have stored in the zero-page.</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="335px" height="120px" viewBox="0 0 335 120" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="2" y="10" class="caption">Mnemonic</text><text class="caption" x="80" y="10">Instruction</text><text class="caption" x="198" y="10">Lookup</text><text class="caption" x="309" y="10">Data</text>
|
|
<text x="2" y="35">LDA ($70),Y</text><text x="95" y="35">B1</text><text x="115" y="35">70</text>
|
|
<rect x="90.5" y="21.5" width="20" height="19" />
|
|
<rect x="110.5" y="21.5" width="20" height="19" />
|
|
<text x="155" y="35">$0070:</text><text x="200" y="35">43</text><text x="220" y="35">35</text>
|
|
<rect x="195.5" y="21.5" width="20" height="19" />
|
|
<rect x="215.5" y="21.5" width="20" height="19" />
|
|
<text x="245" y="60">+ =</text><text x="270" y="60">$3553:</text><text x="315" y="60">23</text>
|
|
<rect x="310.5" y="46.5" width="20" height="19" />
|
|
<text x="198" y="85">Y:</text><text x="220" y="85">10</text>
|
|
<rect x="215.5" y="71.5" width="20" height="19" />
|
|
<text x="293" y="110">A:</text><text x="315" y="110">23</text>
|
|
<rect x="310.5" y="96.5" width="20" height="19" />
|
|
<line x1="320" x2="320" y1="70" y2="85" class="result" />
|
|
<line x1="236" x2="244.5" y1="42" y2="52.5" class="indexed" />
|
|
<line x1="236" x2="244.5" y1="70" y2="59.5" class="indexed" />
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist xwide" aria-label="examples: mnemonic and meaning">
|
|
<dt>LDA ($70),Y</dt><dd>add the contents of the Y-register to the pointer provided in<br />"$0070" and "$0071" and load the contents of this address into A</dd>
|
|
<dt>STA ($A2),Y</dt><dd>store the contents of A in the location given by the pointer<br />in "$00A2" and "$00A3" plus the contents of the Y-register</dd>
|
|
<dt>EOR ($BA),Y</dt><dd>perform an exlusive OR of the contents of A and the address<br />given by the addition of Y to the pointer in "$00BA" and "$00BB"</dd>
|
|
</dl>
|
|
</li>
|
|
<li><h4>Relative Addressing (Conditional Branching)</h4>
|
|
<p>This final address mode is exlusive to conditional branch instructions, which branch in the execution path depending on the state of a given CPU flag. Here, the instruction provides only a relative offset, which is added to the contents of the program counter (PC) as it points to the immediate next instruction. The relative offset is a signed single byte value in two's complement encoding (giving a range of −128…+127), which allows for branching up to half a page forwards and backwards.<br />On the one hand, this makes these instructions compact, fast and relocatable at the same time. On the other hand, we have to mind that our branch target is no farther away than half a memory page.</p>
|
|
<p>Generally, an assembler will take care of this and we only have to provide the target address, not having to worry about relative addressing.</p>
|
|
<p>These instructions are always of 2 bytes length and perform in 2 CPU cycles, if the branch is not taken (the condition resolving to 'false'), and 3 cycles, if the branch is taken (when the condition is true). If a branch is taken and the target is on a different page, this adds another CPU cycle (4 in total).</p>
|
|
<figure class="addressingmode-example">
|
|
<svg x="0px" y="0px" width="335px" height="90px" viewBox="0 0 335 90" role="img" aria-label="Illustration of addressing mode">
|
|
<g class="addrxmp">
|
|
<text x="12" y="10" class="caption">PC</text><text x="84" y="10" class="caption">Mnemonic</text><text class="caption" x="160" y="10">Instruction</text><text class="caption" x="297" y="10">Target</text>
|
|
<text x="2" y="35">$1000</text>
|
|
<text x="2" y="60">$1002</text>
|
|
<text x="80" y="35">BEQ $1005</text><text x="175" y="35">F0</text><text x="195" y="35">03</text>
|
|
<rect x="170.5" y="21.5" width="20" height="19" />
|
|
<rect x="190.5" y="21.5" width="20" height="19" />
|
|
<line x1="34.5" x2="217.5" y1="56.5" y2="66.5" class="indexed" />
|
|
<line x1="210.5" x2="220.5" y1="43.5" y2="60.5" class="indexed" />
|
|
<text x="221" y="70">+</text><text x="275" y="70">PC: $1005</text>
|
|
<line x1="236" x2="258" y1="66" y2="66" class="result" />
|
|
<text x="220" y="51" class="caption">Offset</text>
|
|
<text x="37" y="80" class="caption">PC pointing to next instruction</text>
|
|
</g>
|
|
</svg>
|
|
</figure>
|
|
<p>Mnemonic Examples:</p>
|
|
<dl class="opclist wide" aria-label="examples: mnemonic and meaning">
|
|
<dt>BEQ $1005</dt><dd>branch to location "$1005", if the zero flag is set.<br />if the current address is $1000, this will give an offset of $03.</dd>
|
|
<dt>BCS $08C4</dt><dd>branch to location "$08C4", if the carry flag is set.<br />if the current address is $08D4, this will give an offset of $EE (−$12).</dd>
|
|
<dt>BCC $084A</dt><dd>branch to location "$084A", if the carry flag is clear.</dd>
|
|
</dl>
|
|
</li>
|
|
</ul>
|
|
<h3>Vendor</h3>
|
|
<p>MOS Technology, 1975</p>
|
|
|
|
<figure>
|
|
<img src="assets/MOS_6502AD_4585.jpg" alt="MOS Techology 6502 MPU" title="MOS Techology 6502 MPU" width="400" height="144" style="width: 250px; height: auto;" />
|
|
<p>Image: <a href="https://commons.wikimedia.org/wiki/File:MOS_6502AD_4585_top.jpg" target="_blank" rel="noopener">Wikimedia Commons</a>.</p>
|
|
</figure>
|
|
|
|
<h2 id="details">6502 Instructions in Detail</h2>
|
|
|
|
<dl class="opcodes">
|
|
<dt id="ADC">ADC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Add Memory to Accumulator with Carry</p>
|
|
<p aria-label="synopsis">A + M + C <span aria-label="right-hand transfer">-></span> A, C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>+</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>ADC #oper</td><td>69</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>ADC oper</td><td>65</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>ADC oper,X</td><td>75</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>ADC oper</td><td>6D</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>ADC oper,X</td><td>7D</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>absolute,Y</td><td>ADC oper,Y</td><td>79</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>(indirect,X)</td><td>ADC (oper,X)</td><td>61</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>ADC (oper),Y</td><td>71</td><td>2</td><td>5<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="AND">AND</dt>
|
|
<dd>
|
|
<p aria-label="summary">AND Memory with Accumulator</p>
|
|
<p aria-label="synopsis">A AND M <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>AND #oper</td><td>29</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>AND oper</td><td>25</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>AND oper,X</td><td>35</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>AND oper</td><td>2D</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>AND oper,X</td><td>3D</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>absolute,Y</td><td>AND oper,Y</td><td>39</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>(indirect,X)</td><td>AND (oper,X)</td><td>21</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>AND (oper),Y</td><td>31</td><td>2</td><td>5<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ASL">ASL</dt>
|
|
<dd>
|
|
<p aria-label="summary">Shift Left One Bit (Memory or Accumulator)</p>
|
|
<p aria-label="synopsis">C <span aria-label="left-hand transfer"><-</span> [76543210] <span aria-label="left-hand transfer"><-</span> 0</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>accumulator</td><td>ASL A</td><td>0A</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>ASL oper</td><td>06</td><td>2</td><td>5 </td></tr>
|
|
<tr><td>zeropage,X</td><td>ASL oper,X</td><td>16</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>absolute</td><td>ASL oper</td><td>0E</td><td>3</td><td>6 </td></tr>
|
|
<tr><td>absolute,X</td><td>ASL oper,X</td><td>1E</td><td>3</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BCC">BCC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Carry Clear</p>
|
|
<p aria-label="synopsis">branch on C = 0</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BCC oper</td><td>90</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BCS">BCS</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Carry Set</p>
|
|
<p aria-label="synopsis">branch on C = 1</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BCS oper</td><td>B0</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BEQ">BEQ</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Result Zero</p>
|
|
<p aria-label="synopsis">branch on Z = 1</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BEQ oper</td><td>F0</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BIT">BIT</dt>
|
|
<dd>
|
|
<p aria-label="summary">Test Bits in Memory with Accumulator</p>
|
|
<p aria-label="notes on the implementation">bits 7 and 6 of operand are transfered to bit 7 and 6 of SR (N,V);<br />
|
|
the zero-flag is set according to the result of the operand AND<br />
|
|
the accumulator (set, if the result is zero, unset otherwise).<br />
|
|
This allows a quick check of a few bits at once without affecting<br />
|
|
any of the registers, other than the status register (SR).</p>
|
|
<p aria-label="synopsis">A AND M <span aria-label="right-hand transfer">-></span> Z, M7 <span aria-label="right-hand transfer">-></span> N, M6 <span aria-label="right-hand transfer">-></span> V</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>M7</td><td>+</td><td>-</td><td>-</td><td>-</td><td>M6</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>zeropage</td><td>BIT oper</td><td>24</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>absolute</td><td>BIT oper</td><td>2C</td><td>3</td><td>4 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BMI">BMI</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Result Minus</p>
|
|
<p aria-label="synopsis">branch on N = 1</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BMI oper</td><td>30</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BNE">BNE</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Result not Zero</p>
|
|
<p aria-label="synopsis">branch on Z = 0</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BNE oper</td><td>D0</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BPL">BPL</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Result Plus</p>
|
|
<p aria-label="synopsis">branch on N = 0</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BPL oper</td><td>10</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BRK">BRK</dt>
|
|
<dd>
|
|
<p aria-label="summary">Force Break</p>
|
|
<p aria-label="notes on the implementation">BRK initiates a software interrupt similar to a hardware<br />
|
|
interrupt (IRQ). The return address pushed to the stack is<br />
|
|
PC+2, providing an extra byte of spacing for a break mark<br />
|
|
(identifying a reason for the break.)<br />
|
|
The status register will be pushed to the stack with the break<br />
|
|
flag set to 1. However, when retrieved during RTI or by a PLP<br />
|
|
instruction, the break flag will be ignored.<br />
|
|
The interrupt disable flag is not set automatically.</p>
|
|
<p aria-label="synopsis">interrupt,<br />push PC+2, push SR </p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>1</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>BRK</td><td>00</td><td>1</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BVC">BVC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Overflow Clear</p>
|
|
<p aria-label="synopsis">branch on V = 0</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BVC oper</td><td>50</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="BVS">BVS</dt>
|
|
<dd>
|
|
<p aria-label="summary">Branch on Overflow Set</p>
|
|
<p aria-label="synopsis">branch on V = 1</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>relative</td><td>BVS oper</td><td>70</td><td>2</td><td>2<a href="#opcodes-footnote2" class="footnote" aria-label="see footnote 2" title="add 1 to cycles if branch occurs on same page
add 2 to cycles if branch occurs to different page">**</a></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="CLC">CLC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Clear Carry Flag</p>
|
|
<p aria-label="synopsis">0 <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>0</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>CLC</td><td>18</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="CLD">CLD</dt>
|
|
<dd>
|
|
<p aria-label="summary">Clear Decimal Mode</p>
|
|
<p aria-label="synopsis">0 <span aria-label="right-hand transfer">-></span> D</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>0</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>CLD</td><td>D8</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="CLI">CLI</dt>
|
|
<dd>
|
|
<p aria-label="summary">Clear Interrupt Disable Bit</p>
|
|
<p aria-label="synopsis">0 <span aria-label="right-hand transfer">-></span> I</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>0</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>CLI</td><td>58</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="CLV">CLV</dt>
|
|
<dd>
|
|
<p aria-label="summary">Clear Overflow Flag</p>
|
|
<p aria-label="synopsis">0 <span aria-label="right-hand transfer">-></span> V</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>0</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>CLV</td><td>B8</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="CMP">CMP</dt>
|
|
<dd>
|
|
<p aria-label="summary">Compare Memory with Accumulator</p>
|
|
<p aria-label="synopsis">A - M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>CMP #oper</td><td>C9</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>CMP oper</td><td>C5</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>CMP oper,X</td><td>D5</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>CMP oper</td><td>CD</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>CMP oper,X</td><td>DD</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>absolute,Y</td><td>CMP oper,Y</td><td>D9</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>(indirect,X)</td><td>CMP (oper,X)</td><td>C1</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>CMP (oper),Y</td><td>D1</td><td>2</td><td>5<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="CPX">CPX</dt>
|
|
<dd>
|
|
<p aria-label="summary">Compare Memory and Index X</p>
|
|
<p aria-label="synopsis">X - M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>CPX #oper</td><td>E0</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>CPX oper</td><td>E4</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>absolute</td><td>CPX oper</td><td>EC</td><td>3</td><td>4 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="CPY">CPY</dt>
|
|
<dd>
|
|
<p aria-label="summary">Compare Memory and Index Y</p>
|
|
<p aria-label="synopsis">Y - M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>CPY #oper</td><td>C0</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>CPY oper</td><td>C4</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>absolute</td><td>CPY oper</td><td>CC</td><td>3</td><td>4 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="DEC">DEC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Decrement Memory by One</p>
|
|
<p aria-label="synopsis">M - 1 <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>zeropage</td><td>DEC oper</td><td>C6</td><td>2</td><td>5 </td></tr>
|
|
<tr><td>zeropage,X</td><td>DEC oper,X</td><td>D6</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>absolute</td><td>DEC oper</td><td>CE</td><td>3</td><td>6 </td></tr>
|
|
<tr><td>absolute,X</td><td>DEC oper,X</td><td>DE</td><td>3</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="DEX">DEX</dt>
|
|
<dd>
|
|
<p aria-label="summary">Decrement Index X by One</p>
|
|
<p aria-label="synopsis">X - 1 <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>DEX</td><td>CA</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="DEY">DEY</dt>
|
|
<dd>
|
|
<p aria-label="summary">Decrement Index Y by One</p>
|
|
<p aria-label="synopsis">Y - 1 <span aria-label="right-hand transfer">-></span> Y</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>DEY</td><td>88</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="EOR">EOR</dt>
|
|
<dd>
|
|
<p aria-label="summary">Exclusive-OR Memory with Accumulator</p>
|
|
<p aria-label="synopsis">A EOR M <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>EOR #oper</td><td>49</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>EOR oper</td><td>45</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>EOR oper,X</td><td>55</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>EOR oper</td><td>4D</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>EOR oper,X</td><td>5D</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>absolute,Y</td><td>EOR oper,Y</td><td>59</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>(indirect,X)</td><td>EOR (oper,X)</td><td>41</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>EOR (oper),Y</td><td>51</td><td>2</td><td>5<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="INC">INC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Increment Memory by One</p>
|
|
<p aria-label="synopsis">M + 1 <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>zeropage</td><td>INC oper</td><td>E6</td><td>2</td><td>5 </td></tr>
|
|
<tr><td>zeropage,X</td><td>INC oper,X</td><td>F6</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>absolute</td><td>INC oper</td><td>EE</td><td>3</td><td>6 </td></tr>
|
|
<tr><td>absolute,X</td><td>INC oper,X</td><td>FE</td><td>3</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="INX">INX</dt>
|
|
<dd>
|
|
<p aria-label="summary">Increment Index X by One</p>
|
|
<p aria-label="synopsis">X + 1 <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>INX</td><td>E8</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="INY">INY</dt>
|
|
<dd>
|
|
<p aria-label="summary">Increment Index Y by One</p>
|
|
<p aria-label="synopsis">Y + 1 <span aria-label="right-hand transfer">-></span> Y</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>INY</td><td>C8</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="JMP">JMP</dt>
|
|
<dd>
|
|
<p aria-label="summary">Jump to New Location</p>
|
|
<p aria-label="synopsis">operand 1st byte <span aria-label="right-hand transfer">-></span> PCL<br />operand 2nd byte <span aria-label="right-hand transfer">-></span> PCH</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>absolute</td><td>JMP oper</td><td>4C</td><td>3</td><td>3 </td></tr>
|
|
<tr><td>indirect</td><td>JMP (oper)</td><td>6C</td><td>3</td><td>5 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="JSR">JSR</dt>
|
|
<dd>
|
|
<p aria-label="summary">Jump to New Location Saving Return Address</p>
|
|
<p aria-label="synopsis">push (PC+2),<br />operand 1st byte <span aria-label="right-hand transfer">-></span> PCL<br />operand 2nd byte <span aria-label="right-hand transfer">-></span> PCH</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>absolute</td><td>JSR oper</td><td>20</td><td>3</td><td>6 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="LDA">LDA</dt>
|
|
<dd>
|
|
<p aria-label="summary">Load Accumulator with Memory</p>
|
|
<p aria-label="synopsis">M <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>LDA #oper</td><td>A9</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>LDA oper</td><td>A5</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>LDA oper,X</td><td>B5</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>LDA oper</td><td>AD</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>LDA oper,X</td><td>BD</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>absolute,Y</td><td>LDA oper,Y</td><td>B9</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>(indirect,X)</td><td>LDA (oper,X)</td><td>A1</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>LDA (oper),Y</td><td>B1</td><td>2</td><td>5<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="LDX">LDX</dt>
|
|
<dd>
|
|
<p aria-label="summary">Load Index X with Memory</p>
|
|
<p aria-label="synopsis">M <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>LDX #oper</td><td>A2</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>LDX oper</td><td>A6</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,Y</td><td>LDX oper,Y</td><td>B6</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>LDX oper</td><td>AE</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,Y</td><td>LDX oper,Y</td><td>BE</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="LDY">LDY</dt>
|
|
<dd>
|
|
<p aria-label="summary">Load Index Y with Memory</p>
|
|
<p aria-label="synopsis">M <span aria-label="right-hand transfer">-></span> Y</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>LDY #oper</td><td>A0</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>LDY oper</td><td>A4</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>LDY oper,X</td><td>B4</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>LDY oper</td><td>AC</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>LDY oper,X</td><td>BC</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="LSR">LSR</dt>
|
|
<dd>
|
|
<p aria-label="summary">Shift One Bit Right (Memory or Accumulator)</p>
|
|
<p aria-label="synopsis">0 <span aria-label="right-hand transfer">-></span> [76543210] <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>0</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>accumulator</td><td>LSR A</td><td>4A</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>LSR oper</td><td>46</td><td>2</td><td>5 </td></tr>
|
|
<tr><td>zeropage,X</td><td>LSR oper,X</td><td>56</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>absolute</td><td>LSR oper</td><td>4E</td><td>3</td><td>6 </td></tr>
|
|
<tr><td>absolute,X</td><td>LSR oper,X</td><td>5E</td><td>3</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="NOP">NOP</dt>
|
|
<dd>
|
|
<p aria-label="summary">No Operation</p>
|
|
<p aria-label="synopsis">---</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>NOP</td><td>EA</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ORA">ORA</dt>
|
|
<dd>
|
|
<p aria-label="summary">OR Memory with Accumulator</p>
|
|
<p aria-label="synopsis">A OR M <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>ORA #oper</td><td>09</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>ORA oper</td><td>05</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>ORA oper,X</td><td>15</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>ORA oper</td><td>0D</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>ORA oper,X</td><td>1D</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>absolute,Y</td><td>ORA oper,Y</td><td>19</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>(indirect,X)</td><td>ORA (oper,X)</td><td>01</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>ORA (oper),Y</td><td>11</td><td>2</td><td>5<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="PHA">PHA</dt>
|
|
<dd>
|
|
<p aria-label="summary">Push Accumulator on Stack</p>
|
|
<p aria-label="synopsis">push A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>PHA</td><td>48</td><td>1</td><td>3 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="PHP">PHP</dt>
|
|
<dd>
|
|
<p aria-label="summary">Push Processor Status on Stack</p>
|
|
<p aria-label="notes on the implementation">The status register will be pushed with the break<br />flag and bit 5 set to 1.</p>
|
|
<p aria-label="synopsis">push SR</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>PHP</td><td>08</td><td>1</td><td>3 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="PLA">PLA</dt>
|
|
<dd>
|
|
<p aria-label="summary">Pull Accumulator from Stack</p>
|
|
<p aria-label="synopsis">pull A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>PLA</td><td>68</td><td>1</td><td>4 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="PLP">PLP</dt>
|
|
<dd>
|
|
<p aria-label="summary">Pull Processor Status from Stack</p>
|
|
<p aria-label="notes on the implementation">The status register will be pulled with the break<br />flag and bit 5 ignored.</p>
|
|
<p aria-label="synopsis">pull SR</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td colspan="6">from stack</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>PLP</td><td>28</td><td>1</td><td>4 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ROL">ROL</dt>
|
|
<dd>
|
|
<p aria-label="summary">Rotate One Bit Left (Memory or Accumulator)</p>
|
|
<p aria-label="synopsis">C <span aria-label="left-hand transfer"><-</span> [76543210] <span aria-label="left-hand transfer"><-</span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>accumulator</td><td>ROL A</td><td>2A</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>ROL oper</td><td>26</td><td>2</td><td>5 </td></tr>
|
|
<tr><td>zeropage,X</td><td>ROL oper,X</td><td>36</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>absolute</td><td>ROL oper</td><td>2E</td><td>3</td><td>6 </td></tr>
|
|
<tr><td>absolute,X</td><td>ROL oper,X</td><td>3E</td><td>3</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ROR">ROR</dt>
|
|
<dd>
|
|
<p aria-label="summary">Rotate One Bit Right (Memory or Accumulator)</p>
|
|
<p aria-label="synopsis">C <span aria-label="right-hand transfer">-></span> [76543210] <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>accumulator</td><td>ROR A</td><td>6A</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>ROR oper</td><td>66</td><td>2</td><td>5 </td></tr>
|
|
<tr><td>zeropage,X</td><td>ROR oper,X</td><td>76</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>absolute</td><td>ROR oper</td><td>6E</td><td>3</td><td>6 </td></tr>
|
|
<tr><td>absolute,X</td><td>ROR oper,X</td><td>7E</td><td>3</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="RTI">RTI</dt>
|
|
<dd>
|
|
<p aria-label="summary">Return from Interrupt</p>
|
|
<p aria-label="notes on the implementation">The status register is pulled with the break flag<br />and bit 5 ignored. Then PC is pulled from the stack.</p>
|
|
<p aria-label="synopsis">pull SR, pull PC</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td colspan="6">from stack</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>RTI</td><td>40</td><td>1</td><td>6 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="RTS">RTS</dt>
|
|
<dd>
|
|
<p aria-label="summary">Return from Subroutine</p>
|
|
<p aria-label="synopsis">pull PC, PC+1 <span aria-label="right-hand transfer">-></span> PC</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>RTS</td><td>60</td><td>1</td><td>6 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SBC">SBC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Subtract Memory from Accumulator with Borrow</p>
|
|
<p aria-label="synopsis">A - M - C̅ <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>+</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>immediate</td><td>SBC #oper</td><td>E9</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>SBC oper</td><td>E5</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>SBC oper,X</td><td>F5</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>SBC oper</td><td>ED</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>SBC oper,X</td><td>FD</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>absolute,Y</td><td>SBC oper,Y</td><td>F9</td><td>3</td><td>4<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
<tr><td>(indirect,X)</td><td>SBC (oper,X)</td><td>E1</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>SBC (oper),Y</td><td>F1</td><td>2</td><td>5<a href="#opcodes-footnote1" class="footnote" aria-label="see footnote 1" title="add 1 to cycles if page boundary is crossed">*</a> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SEC">SEC</dt>
|
|
<dd>
|
|
<p aria-label="summary">Set Carry Flag</p>
|
|
<p aria-label="synopsis">1 <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>1</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>SEC</td><td>38</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SED">SED</dt>
|
|
<dd>
|
|
<p aria-label="summary">Set Decimal Flag</p>
|
|
<p aria-label="synopsis">1 <span aria-label="right-hand transfer">-></span> D</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>1</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>SED</td><td>F8</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SEI">SEI</dt>
|
|
<dd>
|
|
<p aria-label="summary">Set Interrupt Disable Status</p>
|
|
<p aria-label="synopsis">1 <span aria-label="right-hand transfer">-></span> I</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>1</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>SEI</td><td>78</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="STA">STA</dt>
|
|
<dd>
|
|
<p aria-label="summary">Store Accumulator in Memory</p>
|
|
<p aria-label="synopsis">A <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>zeropage</td><td>STA oper</td><td>85</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>STA oper,X</td><td>95</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>STA oper</td><td>8D</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>absolute,X</td><td>STA oper,X</td><td>9D</td><td>3</td><td>5 </td></tr>
|
|
<tr><td>absolute,Y</td><td>STA oper,Y</td><td>99</td><td>3</td><td>5 </td></tr>
|
|
<tr><td>(indirect,X)</td><td>STA (oper,X)</td><td>81</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>(indirect),Y</td><td>STA (oper),Y</td><td>91</td><td>2</td><td>6 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="STX">STX</dt>
|
|
<dd>
|
|
<p aria-label="summary">Store Index X in Memory</p>
|
|
<p aria-label="synopsis">X <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>zeropage</td><td>STX oper</td><td>86</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,Y</td><td>STX oper,Y</td><td>96</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>STX oper</td><td>8E</td><td>3</td><td>4 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="STY">STY</dt>
|
|
<dd>
|
|
<p aria-label="summary">Sore Index Y in Memory</p>
|
|
<p aria-label="synopsis">Y <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>zeropage</td><td>STY oper</td><td>84</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>zeropage,X</td><td>STY oper,X</td><td>94</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>absolute</td><td>STY oper</td><td>8C</td><td>3</td><td>4 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="TAX">TAX</dt>
|
|
<dd>
|
|
<p aria-label="summary">Transfer Accumulator to Index X</p>
|
|
<p aria-label="synopsis">A <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>TAX</td><td>AA</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="TAY">TAY</dt>
|
|
<dd>
|
|
<p aria-label="summary">Transfer Accumulator to Index Y</p>
|
|
<p aria-label="synopsis">A <span aria-label="right-hand transfer">-></span> Y</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>TAY</td><td>A8</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="TSX">TSX</dt>
|
|
<dd>
|
|
<p aria-label="summary">Transfer Stack Pointer to Index X</p>
|
|
<p aria-label="synopsis">SP <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>TSX</td><td>BA</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="TXA">TXA</dt>
|
|
<dd>
|
|
<p aria-label="summary">Transfer Index X to Accumulator</p>
|
|
<p aria-label="synopsis">X <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>TXA</td><td>8A</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="TXS">TXS</dt>
|
|
<dd>
|
|
<p aria-label="summary">Transfer Index X to Stack Register</p>
|
|
<p aria-label="synopsis">X <span aria-label="right-hand transfer">-></span> SP</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>TXS</td><td>9A</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="TYA">TYA</dt>
|
|
<dd>
|
|
<p aria-label="summary">Transfer Index Y to Accumulator</p>
|
|
<p aria-label="synopsis">Y <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>implied</td><td>TYA</td><td>98</td><td>1</td><td>2 </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
<dl class="footnotes footnotes-opcodes" aria-label="footnotes regarding opcode cycles">
|
|
<dt id="opcodes-footnote1" aria-label="footnote 1">* </dt><dd>add 1 to cycles if page boundary is crossed</dd>
|
|
<dt id="opcodes-footnote2" aria-label="footnote 2">**</dt><dd>add 1 to cycles if branch occurs on same page<br />
|
|
add 2 to cycles if branch occurs to different page</dd>
|
|
</dl>
|
|
|
|
<p class="opcodes-legend">Legend to Flags:</p>
|
|
<dl class="opcodes opcodes-legend-list" aria-label="list of flag symbols and their respective meaning">
|
|
<dt>+</dt><dd>modified</dd>
|
|
<dt>-</dt><dd>not modified</dd>
|
|
<dt>1</dt><dd>set</dd>
|
|
<dt>0</dt><dd>cleared</dd>
|
|
<dt>M6</dt><dd>memory bit 6</dd>
|
|
<dt>M7</dt><dd>memory bit 7</dd>
|
|
</dl>
|
|
|
|
<p>Note on assembler syntax:<br />
|
|
Some assemblers employ "OPC *oper" or a ".b" extension to the mneomonic for<br />forced zeropage addressing.</p>
|
|
|
|
<p id="read_modify_write">Note on Read-Modify-Write instructions <i>(NMOS 6502 only)</i>:<br />
|
|
Some instructions like EOR, ASL, ROL, DEC, INC, etc., fetch a value from memory<br />
|
|
to modify it and to write the modified value back to the originating address.<br />
|
|
The original NMOS 6502 switches immediately into write mode after the read of<br />
|
|
the value, resulting in the unmodified value being written back to the address<br />
|
|
(while the value is modified in the next cycle), before the modified value is<br />
|
|
finally written to the destination. This may cause issues when writing to<br />
|
|
devices attached to the address bus that may trigger some action on this<br />
|
|
intermediate write operation.<br />
|
|
This does not apply to the CMOS variants of the 6502.</p>
|
|
|
|
|
|
<h2 id="illegals">"Illegal" Opcodes and Undocumented Instructions</h2>
|
|
<div class="explanation illegals-remarks">
|
|
<p>The following instructions are undocumented are not guaranteed to work.<br />
|
|
Some are highly unstable, some may even start two asynchronous threads competing in race condition with the winner determined by such miniscule factors as temperature or minor differences in the production series, at other times, the outcome depends on the exact values involved and the chip series.</p>
|
|
<p>Use with care and at your own risk.</p>
|
|
<p>There are several mnemonics for various opcodes. Here, they are (mostly) the same as those used by the ACME and DASM assemblers with known synonyms provided in parentheses:</p>
|
|
|
|
<ul class="flow narrow" aria-label="list of mnemonics commonly used for illegal opcodes">
|
|
<li><a href="#ALR" title="instruction details for ALR..."><span class="dotted">ALR</span> (ASR)</a></li>
|
|
<li><a href="#ANC" title="instruction details for ANC..."><span class="dotted">ANC</span></a></li>
|
|
<li><a href="#ANC2" title="instruction details for ANC..."><span class="dotted">ANC</span> (ANC2)</a></li>
|
|
<li><a href="#ANE" title="instruction details for ANE..."><span class="dotted">ANE</span> (XAA)</a></li>
|
|
<li><a href="#ARR" title="instruction details for ARR..."><span class="dotted">ARR</span></a></li>
|
|
<li><a href="#DCP" title="instruction details for DCP..."><span class="dotted">DCP</span> (DCM)</a></li>
|
|
<li><a href="#ISC" title="instruction details for ISC..."><span class="dotted">ISC</span> (ISB, INS)</a></li>
|
|
<li><a href="#LAS" title="instruction details for LAS..."><span class="dotted">LAS</span> (LAR)</a></li>
|
|
<li><a href="#LAX" title="instruction details for LAX..."><span class="dotted">LAX</span></a></li>
|
|
<li><a href="#LXA" title="instruction details for LXA..."><span class="dotted">LXA</span> (LAX immediate)</a></li>
|
|
<li><a href="#RLA" title="instruction details for RLA..."><span class="dotted">RLA</span></a></li>
|
|
<li><a href="#RRA" title="instruction details for RRA..."><span class="dotted">RRA</span></a></li>
|
|
<li><a href="#SAX" title="instruction details for SAX..."><span class="dotted">SAX</span> (AXS, AAX)</a></li>
|
|
<li><a href="#SBX" title="instruction details for SBX..."><span class="dotted">SBX</span> (AXS, SAX)</a></li>
|
|
<li><a href="#SHA" title="instruction details for SHA..."><span class="dotted">SHA</span> (AHX, AXA)</a></li>
|
|
<li><a href="#SHX" title="instruction details for SHX..."><span class="dotted">SHX</span> (A11, SXA, XAS)</a></li>
|
|
<li><a href="#SHY" title="instruction details for SHY..."><span class="dotted">SHY</span> (A11, SYA, SAY)</a></li>
|
|
<li><a href="#SLO" title="instruction details for SLO..."><span class="dotted">SLO</span> (ASO)</a></li>
|
|
<li><a href="#SRE" title="instruction details for SRE..."><span class="dotted">SRE</span> (LSE)</a></li>
|
|
<li><a href="#TAS" title="instruction details for TAS..."><span class="dotted">TAS</span> (XAS, SHS)</a></li>
|
|
<li><a href="#USBC" title="instruction details for USBC..."><span class="dotted">USBC</span> (SBC)</a></li>
|
|
<li><a href="#NOPs" title="instruction details for NOPs..."><span class="dotted">NOPs</span> (including DOP, TOP)</a></li>
|
|
<li><a href="#JAM" title="instruction details for JAM..."><span class="dotted">JAM</span> (KIL, HLT)</a></li>
|
|
</ul>
|
|
|
|
<h3>"Illegal" Opcodes in Details</h3>
|
|
<p>Legend to markers used in the instruction details:</p>
|
|
<dl class="footnotes footnotes-opcodes illegals" aria-label="legend to footnotes and markers">
|
|
<dt>* </dt><dd>add 1 to cycles if page boundary is crossed</dd>
|
|
<dt class="warn">†</dt><dd>unstable</dd>
|
|
<dt class="warn">††</dt><dd>highly unstable</dd>
|
|
</dl>
|
|
</div>
|
|
|
|
<dl class="opcodes illegals">
|
|
<dt id="ALR">ALR (ASR)</dt>
|
|
<dd>
|
|
<p aria-label="summary">AND oper + LSR</p>
|
|
<p aria-label="synopsis">A AND oper, 0 <span aria-label="right-hand transfer">-></span> [76543210] <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>ALR #oper</td><td>4B</td><td>2</td><td>2 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ANC">ANC</dt>
|
|
<dd>
|
|
<p aria-label="summary">AND oper + set C as ASL</p>
|
|
<p aria-label="synopsis">A AND oper, bit(7) <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>ANC #oper</td><td>0B</td><td>2</td><td>2 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ANC2">ANC (ANC2)</dt>
|
|
<dd>
|
|
<p aria-label="summary">AND oper + set C as ROL</p>
|
|
<p aria-label="summary">effectively the same as instr. 0B</p>
|
|
<p aria-label="synopsis">A AND oper, bit(7) <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>ANC #oper</td><td>2B</td><td>2</td><td>2 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ANE">ANE (XAA)</dt>
|
|
<dd>
|
|
<p aria-label="summary">* OR X + AND oper</p>
|
|
Highly unstable, do not use.</p>
|
|
<p aria-label="notes">A base value in A is determined based on the contets of A and a constant, which may be typically $00, $ff, $ee, etc. The value of this constant depends on temerature, the chip series, and maybe other factors, as well.<br />
|
|
In order to eliminate these uncertaincies from the equation, use either 0 as the operand or a value of $FF in the accumulator.</p>
|
|
<p aria-label="synopsis">(A OR CONST) AND X AND oper <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>ANE #oper</td><td>8B</td><td>2</td><td>2 </td><td title="highly unstable" style="cursor: default;">††</td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ARR">ARR</dt>
|
|
<dd>
|
|
<p aria-label="summary">AND oper + ROR</p>
|
|
<p aria-label="notes">This operation involves the adder:<br />
|
|
V-flag is set according to (A AND oper) + oper<br />
|
|
The carry is not set, but bit 7 (sign) is exchanged with the carry</p>
|
|
<p aria-label="synopsis">A AND oper, C <span aria-label="right-hand transfer">-></span> [76543210] <span aria-label="right-hand transfer">-></span> C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>+</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>ARR #oper</td><td>6B</td><td>2</td><td>2 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="DCP">DCP (DCM)</dt>
|
|
<dd>
|
|
<p aria-label="summary">DEC oper + CMP oper</p>
|
|
<p aria-label="synopsis">M - 1 <span aria-label="right-hand transfer">-></span> M, A - M</p>
|
|
<p aria-label="notes">Decrements the operand and then compares the result to the accumulator.</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>DCP oper</td><td>C7</td><td>2</td><td>5 </td><td></td></tr>
|
|
<tr><td>zeropage,X</td><td>DCP oper,X</td><td>D7</td><td>2</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>DCP oper</td><td>CF</td><td>3</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolut,X</td><td>DCP oper,X</td><td>DF</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>absolut,Y</td><td>DCP oper,Y</td><td>DB</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>DCP (oper,X)</td><td>C3</td><td>2</td><td>8 </td><td></td></tr>
|
|
<tr><td>(indirect),Y</td><td>DCP (oper),Y</td><td>D3</td><td>2</td><td>8 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="ISC">ISC (ISB, INS)</dt>
|
|
<dd>
|
|
<p aria-label="summary">INC oper + SBC oper</p>
|
|
<p aria-label="synopsis">M + 1 <span aria-label="right-hand transfer">-></span> M, A - M - C̅ <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>+</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>ISC oper</td><td>E7</td><td>2</td><td>5 </td><td></td></tr>
|
|
<tr><td>zeropage,X</td><td>ISC oper,X</td><td>F7</td><td>2</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>ISC oper</td><td>EF</td><td>3</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolut,X</td><td>ISC oper,X</td><td>FF</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>absolut,Y</td><td>ISC oper,Y</td><td>FB</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>ISC (oper,X)</td><td>E3</td><td>2</td><td>8 </td><td></td></tr>
|
|
<tr><td>(indirect),Y</td><td>ISC (oper),Y</td><td>F3</td><td>2</td><td>8 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="LAS">LAS (LAR)</dt>
|
|
<dd>
|
|
<p aria-label="summary">LDA/TSX oper</p>
|
|
<p aria-label="synopsis">M AND SP <span aria-label="right-hand transfer">-></span> A, X, SP</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>absolut,Y</td><td>LAS oper,Y</td><td>BB</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="LAX">LAX</dt>
|
|
<dd>
|
|
<p aria-label="summary">LDA oper + LDX oper</p>
|
|
<p aria-label="synopsis">M <span aria-label="right-hand transfer">-></span> A <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>LAX oper</td><td>A7</td><td>2</td><td>3 </td><td></td></tr>
|
|
<tr><td>zeropage,Y</td><td>LAX oper,Y</td><td>B7</td><td>2</td><td>4 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>LAX oper</td><td>AF</td><td>3</td><td>4 </td><td></td></tr>
|
|
<tr><td>absolut,Y</td><td>LAX oper,Y</td><td>BF</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>LAX (oper,X)</td><td>A3</td><td>2</td><td>6 </td><td></td></tr>
|
|
<tr><td>(indirect),Y</td><td>LAX (oper),Y</td><td>B3</td><td>2</td><td>5<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="LXA">LXA (LAX immediate)</dt>
|
|
<dd>
|
|
<p aria-label="summary">Store <span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> AND oper in A and X</p>
|
|
<p aria-label="notes">Highly unstable, involves a 'magic' constant, see ANE</p>
|
|
<p aria-label="synopsis">(A OR CONST) AND oper <span aria-label="right-hand transfer">-></span> A <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>LXA #oper</td><td>AB</td><td>2</td><td>2 </td><td title="highly unstable" style="cursor: default;">††</td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="RLA">RLA</dt>
|
|
<dd>
|
|
<p aria-label="summary">ROL oper + AND oper</p>
|
|
<p aria-label="synopsis">M = C <span aria-label="left-hand transfer"><-</span> [76543210] <span aria-label="left-hand transfer"><-</span> C, A AND M <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>RLA oper</td><td>27</td><td>2</td><td>5 </td><td></td></tr>
|
|
<tr><td>zeropage,X</td><td>RLA oper,X</td><td>37</td><td>2</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>RLA oper</td><td>2F</td><td>3</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolut,X</td><td>RLA oper,X</td><td>3F</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>absolut,Y</td><td>RLA oper,Y</td><td>3B</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>RLA (oper,X)</td><td>23</td><td>2</td><td>8 </td><td></td></tr>
|
|
<tr><td>(indirect),Y</td><td>RLA (oper),Y</td><td>33</td><td>2</td><td>8 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="RRA">RRA</dt>
|
|
<dd>
|
|
<p aria-label="summary">ROR oper + ADC oper</p>
|
|
<p aria-label="synopsis">M = C <span aria-label="right-hand transfer">-></span> [76543210] <span aria-label="right-hand transfer">-></span> C, A + M + C <span aria-label="right-hand transfer">-></span> A, C</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>+</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>RRA oper</td><td>67</td><td>2</td><td>5 </td><td></td></tr>
|
|
<tr><td>zeropage,X</td><td>RRA oper,X</td><td>77</td><td>2</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>RRA oper</td><td>6F</td><td>3</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolut,X</td><td>RRA oper,X</td><td>7F</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>absolut,Y</td><td>RRA oper,Y</td><td>7B</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>RRA (oper,X)</td><td>63</td><td>2</td><td>8 </td><td></td></tr>
|
|
<tr><td>(indirect),Y</td><td>RRA (oper),Y</td><td>73</td><td>2</td><td>8 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SAX">SAX (AXS, AAX)</dt>
|
|
<dd>
|
|
<p aria-label="summary">A and X are put on the bus at the same time (resulting effectively in an AND operation) and stored in M</p>
|
|
<p aria-label="synopsis">A AND X <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>SAX oper</td><td>87</td><td>2</td><td>3 </td><td></td></tr>
|
|
<tr><td>zeropage,Y</td><td>SAX oper,Y</td><td>97</td><td>2</td><td>4 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>SAX oper</td><td>8F</td><td>3</td><td>4 </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>SAX (oper,X)</td><td>83</td><td>2</td><td>6 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SBX">SBX (AXS, SAX)</dt>
|
|
<dd>
|
|
<p aria-label="summary">CMP and DEX at once, sets flags like CMP</p>
|
|
<p aria-label="synopsis">(A AND X) - oper <span aria-label="right-hand transfer">-></span> X</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>SBX #oper</td><td>CB</td><td>2</td><td>2 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SHA">SHA (AHX, AXA)</dt>
|
|
<dd>
|
|
<p aria-label="summary">Stores A AND X AND (high-byte of addr. + 1) at addr.</p>
|
|
<p aria-label="notes">unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work (with the high-byte of the value used as the high-byte of the address)</p>
|
|
<p aria-label="synopsis">A AND X AND (H+1) <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>absolut,Y</td><td>SHA oper,Y</td><td>9F</td><td>3</td><td>5 </td><td title="unstable" style="cursor: default;">†</td></tr>
|
|
<tr><td>(indirect),Y</td><td>SHA (oper),Y</td><td>93</td><td>2</td><td>6 </td><td title="unstable" style="cursor: default;">†</td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SHX">SHX (A11, SXA, XAS)</dt>
|
|
<dd>
|
|
<p aria-label="summary">Stores X AND (high-byte of addr. + 1) at addr.</p>
|
|
<p aria-label="notes">unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work (with the high-byte of the value used as the high-byte of the address)</p>
|
|
<p aria-label="synopsis">X AND (H+1) <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>absolut,Y</td><td>SHX oper,Y</td><td>9E</td><td>3</td><td>5 </td><td title="unstable" style="cursor: default;">†</td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SHY">SHY (A11, SYA, SAY)</dt>
|
|
<dd>
|
|
<p aria-label="summary">Stores Y AND (high-byte of addr. + 1) at addr.</p>
|
|
<p aria-label="notes">unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work (with the high-byte of the value used as the high-byte of the address)</p>
|
|
<p aria-label="synopsis">Y AND (H+1) <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>absolut,X</td><td>SHY oper,X</td><td>9C</td><td>3</td><td>5 </td><td title="unstable" style="cursor: default;">†</td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SLO">SLO (ASO)</dt>
|
|
<dd>
|
|
<p aria-label="symmary">ASL oper + ORA oper</p>
|
|
<p aria-label="synopsis">M = C <span aria-label="left-hand transfer"><-</span> [76543210] <span aria-label="left-hand transfer"><-</span> 0, A OR M <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>SLO oper</td><td>07</td><td>2</td><td>5 </td><td></td></tr>
|
|
<tr><td>zeropage,X</td><td>SLO oper,X</td><td>17</td><td>2</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>SLO oper</td><td>0F</td><td>3</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolut,X</td><td>SLO oper,X</td><td>1F</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>absolut,Y</td><td>SLO oper,Y</td><td>1B</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>SLO (oper,X)</td><td>03</td><td>2</td><td>8 </td><td></td></tr>
|
|
<tr><td>(indirect),Y</td><td>SLO (oper),Y</td><td>13</td><td>2</td><td>8 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="SRE">SRE (LSE)</dt>
|
|
<dd>
|
|
<p aria-label="summary">LSR oper + EOR oper</p>
|
|
<p aria-label="synopsis">M = 0 <span aria-label="right-hand transfer">-></span> [76543210] <span aria-label="right-hand transfer">-></span> C, A EOR M <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>zeropage</td><td>SRE oper</td><td>47</td><td>2</td><td>5 </td><td></td></tr>
|
|
<tr><td>zeropage,X</td><td>SRE oper,X</td><td>57</td><td>2</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolute</td><td>SRE oper</td><td>4F</td><td>3</td><td>6 </td><td></td></tr>
|
|
<tr><td>absolut,X</td><td>SRE oper,X</td><td>5F</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>absolut,Y</td><td>SRE oper,Y</td><td>5B</td><td>3</td><td>7 </td><td></td></tr>
|
|
<tr><td>(indirect,X)</td><td>SRE (oper,X)</td><td>43</td><td>2</td><td>8 </td><td></td></tr>
|
|
<tr><td>(indirect),Y</td><td>SRE (oper),Y</td><td>53</td><td>2</td><td>8 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="TAS">TAS (XAS, SHS)</dt>
|
|
<dd>
|
|
<p aria-label="summary">Puts A AND X in SP and stores A AND X AND (high-byte of addr. + 1) at addr.</p>
|
|
<p aria-label="notes">unstable: sometimes 'AND (H+1)' is dropped, page boundary crossings may not work (with the high-byte of the value used as the high-byte of the address)</p>
|
|
<p aria-label="synopsis">A AND X <span aria-label="right-hand transfer">-></span> SP, A AND X AND (H+1) <span aria-label="right-hand transfer">-></span> M</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>absolut,Y</td><td>TAS oper,Y</td><td>9B</td><td>3</td><td>5 </td><td title="unstable" style="cursor: default;">†</td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="USBC">USBC (SBC)</dt>
|
|
<dd>
|
|
<p aria-label="summary">SBC oper + NOP</p>
|
|
<p aria-label="notes">effectively same as normal SBC immediate, instr. E9.</p>
|
|
<p aria-label="synopsis">A - M - C̅ <span aria-label="right-hand transfer">-></span> A</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>+</td><td>-</td><td>-</td><td>+</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th><th></th></tr>
|
|
<tr><td>immediate</td><td>USBC #oper</td><td>EB</td><td>2</td><td>2 </td><td></td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="NOPs">NOPs (including DOP, TOP)</dt>
|
|
<dd>
|
|
<p aria-label="summary">Instructions effecting in 'no operations' in various address modes. Operands are ignored.</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details" class="nops">
|
|
<tr><th>opc</th><th>addressing</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>1A</td><td>implied</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>3A</td><td>implied</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>5A</td><td>implied</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>7A</td><td>implied</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>DA</td><td>implied</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>FA</td><td>implied</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>80</td><td>immediate</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>82</td><td>immediate</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>89</td><td>immediate</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>C2</td><td>immediate</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>E2</td><td>immediate</td><td>2</td><td>2 </td></tr>
|
|
<tr><td>04</td><td>zeropage</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>44</td><td>zeropage</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>64</td><td>zeropage</td><td>2</td><td>3 </td></tr>
|
|
<tr><td>14</td><td>zeropage,X</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>34</td><td>zeropage,X</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>54</td><td>zeropage,X</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>74</td><td>zeropage,X</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>D4</td><td>zeropage,X</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>F4</td><td>zeropage,X</td><td>2</td><td>4 </td></tr>
|
|
<tr><td>0C</td><td>absolute</td><td>3</td><td>4 </td></tr>
|
|
<tr><td>1C</td><td>absolut,X</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td></tr>
|
|
<tr><td>3C</td><td>absolut,X</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td></tr>
|
|
<tr><td>5C</td><td>absolut,X</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td></tr>
|
|
<tr><td>7C</td><td>absolut,X</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td></tr>
|
|
<tr><td>DC</td><td>absolut,X</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td></tr>
|
|
<tr><td>FC</td><td>absolut,X</td><td>3</td><td>4<span title="add 1 to cycles if page boundary is crossed" style="cursor: default;">*</span> </td></tr>
|
|
</table>
|
|
</dd>
|
|
|
|
<dt id="JAM">JAM (KIL, HLT)</dt>
|
|
<dd>
|
|
<p aria-label="summary">These instructions freeze the CPU.</p>
|
|
<p aria-label="notes">The processor will be trapped infinitely in T1 phase with $FF on the data bus. — Reset required.</p>
|
|
<p>Instruction codes: 02, 12, 22, 32, 42, 52, 62, 72, 92, B2, D2, F2</p>
|
|
</dd>
|
|
</dl>
|
|
|
|
<p>Have a look at this <a href="#layout-2-3">table of the instruction layout</a> in order to see how most of these<br />"illegal" instructions are a result of executing both instructions at <em>c=1</em> and <em>c=2</em> in<br />a given slot (same column, rows immediately above) at once.<br />Where <em>c</em> is the lowest two bits of the instruction code. E.g., "SAX abs", instruction<br />code $8F, binary 100011<strong>11</strong>, is "STA abs", 100011<strong>01</strong> ($8D) and "STX abs", 100011<strong>10</strong> ($8E).</p>
|
|
|
|
<h3 id="ror-bug">Honorable Mention: Rev. A 6502 ROR, Pre-June 1976</h3>
|
|
<p style="text-indent: 2em;">Famously, the Rev. A 6502 as delivered from September 1975 to June 1976 had a<br />
|
|
<em>"ROR bug".</em> However, the "ROR" instruction isn't only missing from the original<br />
|
|
documentation, as it turns out, the chip is actually <a href="https://www.youtube.com/watch?v=Uk_QC1eU0Fg" target="_blank" rel="noopener" title="YouTube video: "The 6502 Rotate Right Myth" by @TubeTimeUS">missing crucial control lines</a>,<br />
|
|
which would have been required to make this instruction work. The instruction is<br />
|
|
simply not implemented and it wasn't even part of the design. (This was actually<br />
|
|
added on popular demand in Rev. B, as rumor has it, demand by Steve Wozniak. Even,<br >
|
|
if not true, this makes for a good story. And how could there be a page on the 6502<br />
|
|
without mentioning "Woz" once?) So, for all means, "ROR" is an undocumented or<br />
|
|
"illegal" instruction on the Rev. A 6502.</p>
|
|
<p>And this is how <code>ROR</code> behaves on these Rev. A chips, much like <code>ASL</code>: it shifts all bits<br />
|
|
to the left, shifting in a zero bit at the LSB side, but, unlike <code>ASL</code>, it does not<br />
|
|
shift the high-bit into the carry. (So there are no connections to the carry at all.)</p>
|
|
|
|
<dl class="opcodes illegals">
|
|
<dd>
|
|
<dt id="TAS">ROR Rev. A (pre-June 1976)</dt><dd>
|
|
<p aria-label="summary">As ASL, but does not update the carry.</p>
|
|
<p aria-label="notes">N and Z flags are set correctly for the operation performed.</p>
|
|
<p aria-label="synopsis">[76543210] <span aria-label="left-hand transfer"><-</span> 0</p>
|
|
<table aria-label="flags">
|
|
<tr><th>N</th><th>Z</th><th>C</th><th>I</th><th>D</th><th>V</th></tr>
|
|
<tr><td>+</td><td>+</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
|
|
</table>
|
|
<table aria-label="details">
|
|
<tr><th>addressing</th><th>assembler</th><th>opc</th><th>bytes</th><th>cycles</th></tr>
|
|
<tr><td>accumulator</td><td>ROR A</td><td>6A</td><td>1</td><td>2 </td></tr>
|
|
<tr><td>zeropage</td><td>ROR oper</td><td>66</td><td>2</td><td>5 </td></tr>
|
|
<tr><td>zeropage,X</td><td>ROR oper,X</td><td>76</td><td>2</td><td>6 </td></tr>
|
|
<tr><td>absolute</td><td>ROR oper</td><td>6E</td><td>3</td><td>6 </td></tr>
|
|
<tr><td>absolute,X</td><td>ROR oper,X</td><td>7E</td><td>3</td><td>7 </td></tr>
|
|
</table>
|
|
</dd>
|
|
</dl>
|
|
|
|
<h2 id="compare">Compare Instructions</h2>
|
|
<p class="explanation">The 6502 MPU features three basic compare instructions in various address modes:</p>
|
|
|
|
<table class="compare">
|
|
<thead>
|
|
<tr>
|
|
<th>Instruction</th><th>Comparison</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td><a href="#CMP">CMP</a></td><td>Accumulator and operand</td>
|
|
</tr>
|
|
<tr>
|
|
<td><a href="#CPX">CPX</a></td><td>X register and operand</td>
|
|
</tr>
|
|
<tr>
|
|
<td><a href="#CPY">CPY</a></td><td>Y register and operand</td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
|
|
<p class="explanation">The various compare instructions subtract the operand from the respective register<br />
|
|
(as if the carry was set) without setting the result and adjust the N, Z, and C<br />flags accordingly to this operation.<br />Flags will be set as follows:</p>
|
|
|
|
<table class="compare">
|
|
<thead>
|
|
<tr>
|
|
<th>Relation</th><th title="zero flag">Z</th><th title="carry">C</th><th title="negative flag">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>register < operand</td><td>0</td><td>0</td><td><em>sign-bit of result</em></td>
|
|
</tr>
|
|
<tr>
|
|
<td>register = operand</td><td>1</td><td>1</td><td>0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>register > operand</td><td>0</td><td>1</td><td><em>sign-bit of result</em></td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
|
|
<p class="explanation" style="margin-top: 2em;">And for the derivative relations <em>"less/greater than or equal"</em>:</p>
|
|
|
|
<table class="compare">
|
|
<thead>
|
|
<tr>
|
|
<th>Relation</th><th title="zero flag">Z</th><th title="carry">C</th><th title="negative flag">N</th>
|
|
</tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr>
|
|
<td>register ≤ operand</td><td>1</td><td>0</td><td><em>sign-bit of result</em></td>
|
|
</tr>
|
|
<tr>
|
|
<td>register ≥ operand</td><td>1</td><td>1</td><td><em>sign-bit of result</em></td>
|
|
</tr>
|
|
</tbody>
|
|
</table>
|
|
<p class="explanation">Mind that the negative flag is not significant and all conditions may be evaluated<br />by checking the carry and/or zero flag(s).</p>
|
|
|
|
<h3 id="compare">The BIT Instruction</h3>
|
|
<div class="explanation">
|
|
<p>The <a href="#BIT">BIT</a> instruction may be the most obscure instruction of the 6502:<br />
|
|
While other instruction serve a very clear purpose, like transferring values or<br />
|
|
performing basic arithmetic or logical operations, this one serves a rather<br />
|
|
specialized purpose, but it does so in a very general way.<br />This purpose is bit testing.</p>
|
|
<p>Generally, testing of a particular bit is achieved by masking (isolating) this<br />
|
|
bit (or multiple bits) by an AND operation and then checking the zero flag (Z) by<br />
|
|
a BNE or BEQ instruction. This, however, destroys the contents of the accumulator.<br />
|
|
This is, where the BIT instruction comes in: much like the comparisons perform a<br />
|
|
subtraction without setting the result, the BIT instruction performs a logical AND<br />
|
|
without setting the result, but still reflects the result in the state of the zero<br />
|
|
flag (Z). Which allows for the same checks using the BNE or BEQ instructions,<br />
|
|
without affecting the contents of the accumulator.</p>
|
|
<p>Since the sign-bit is often used as a flag, testing this is also covered by the BIT<br />
|
|
instruction, which additionally to setting the zero flag also transfers bits 7 and 6<br />
|
|
of the operand into the corresponding bits of the status register — which happen to<br />
|
|
be the negative (N) and overflow (V) flags. Therefore, bits 7 and 6 of the operand<br />
|
|
may be tested independently using the BMI/BPL and BVS/BVC instructions.</p>
|
|
<p class="explanation-xmp">
|
|
accumulator operand
|
|
[76543210] AND [76543210] == 0?
|
|
↓↓ ↓
|
|
NV Z
|
|
</p>
|
|
</div>
|
|
|
|
<h2 id="arithmetic">A Primer of 6502 Arithmetic Operations</h2>
|
|
<div class="explanation">
|
|
<p>The 6502 processor features two basic arithmetic instructions, <code>ADC</code>, <em>ADd with Carry</em>,<br />
|
|
and <code>SBC</code>, <em>SuBtract with Carry</em>. As the names suggest, these provide addition and<br />
|
|
subtraction for single byte operands and results. However, operations are not<br />
|
|
limited to a single byte range, which is where the carry flag comes in, providing<br />
|
|
the means for a single-bit carry (or borrow), to combine operations over several<br />
|
|
bytes.</p>
|
|
<p>In order to accomplish this, the carry is included in each of these operations:<br />
|
|
for additions, it is added (much like another operand); for subtractions, which are<br />
|
|
just an addition using the inverse of the operand (complement value of the operand),<br />
|
|
the role of the carry is inverted, as well.<br />
|
|
Therefore, it is crucial to set up the carry appropriatly: fo additions, the carry<br />
|
|
has to be initially cleared (using <code>CLC</code>), while for subtractions, it must be initally<br />set (using <code>SEC</code> — more on <code>SBC</code> below).</p>
|
|
<p class="explanation-xmp"> ;ADC: A = A + M + C
|
|
CLC ;clear carry in preparation
|
|
LDA #2 ;load 2 into the accumulator
|
|
ADD #3 ;add 3 -> now 5 in accumulator
|
|
|
|
;SBC: A = A - M - C̅ ("C̅": "not carry")
|
|
SEC ;set carry in preparation
|
|
LDA #15 ;load 15 into the accumulator
|
|
SBC #8 ;subtract 8 -> now 7 in accumulator</p>
|
|
|
|
<p style="text-indent: -1.25em; padding-left: 1.25em;"><em>Note:</em> Here, we used immediate mode, indicated by the prefix "#" before the operand,<br />
|
|
to directly load a literal value. If there is no such "#" prefix, we generally<br />
|
|
mean to use the value stored at the address, which is given by the operand. As<br />
|
|
we will see in the next example.)</p>
|
|
|
|
<p>To combine this for 16-bit values (2 bytes each), we simply chain the instructions<br />
|
|
for the next bytes to operate on, but this time without setting or clearing the carry.</p>
|
|
<p>Supposing the following locations for storing 16-bit values:</p>
|
|
<p class="explanation-xmp"> low-byte high-byte
|
|
|
|
first argument .... $1000 $1001
|
|
|
|
second argument ... $1002 $1003
|
|
|
|
result ............ $1004 $1005
|
|
</p>
|
|
<p>we perform a 16-bit addition by:</p>
|
|
<p class="explanation-xmp">CLC ;prepare carry for addition
|
|
LDA $1000 ;load value at address $1000 into A (low byte of first argument)
|
|
ADC $1002 ;add low byte of second argument at $1002
|
|
STA $1004 ;store low byte of result at $1004
|
|
LDA $1001 ;load high byte of first argument
|
|
ADC $1003 ;add high byte of second argument
|
|
STA $1005 ;store high byte of result (result in $1004 and $1005)</p>
|
|
<p>and, conversely, for a 16-bit subtraction:</p>
|
|
<p class="explanation-xmp">SEC ;prepare carry for subtraction
|
|
LDA $1000 ;load value at address $1000 into A (low byte of first argument)
|
|
SBC $1002 ;subtract low byte of second argument at $1002
|
|
STA $1004 ;store low byte of result at $1004
|
|
LDA $1001 ;load high byte of first argument
|
|
SBC $1003 ;subtract high byte of second argument
|
|
STA $1005 ;store high byte of result (result in $1004 and $1005)</p>
|
|
|
|
<p style="text-indent: -1.25em; padding-left: 1.25em;"><em>Note:</em> Another, important preparatory step is to set the processor into binary<br />
|
|
mode by use of the <code>CLD</code> <em>(CLear Decimal flag)</em> instruction. (Compare the section<br />
|
|
on decimal mode below.) This has to be done only once.</p>
|
|
|
|
<h3>Signed Values</h3>
|
|
<p>Operations for unsigned and signed values are principally the same, the only<br />
|
|
difference being in how we interpret the values. Generally, the 6502 uses what<br />
|
|
is known as <em>two's complement</em> to represent negative values.</p>
|
|
<p>(In earlier computers,something known as ones' complement was used, where we<br />
|
|
simply flip all bits to their opposite state to represent a negative value.<br />
|
|
While simple, this came with a few drawbacks, like an additional value of<br />
|
|
negative zero, which are overcome by two's complement.)</p>
|
|
<p>In two's complement representation, we simply flip all the bits in a byte to<br />
|
|
their opposite (the same as an XOR by <code>$FF</code>) and then add 1 to this.</p>
|
|
|
|
<p>E.g., to represent -4:,<br />
|
|
(We here use "$" to indicate a hexadecimal number and "%" for binary notation.<br />
|
|
A dot is used to separate the high- and low-nibble, i.e. group of 4 bits.)</p>
|
|
<p class="explanation-xmp"> %0000.0100 4
|
|
XOR %1111.1111 255
|
|
-------------
|
|
%1111.1011 complement (all bits flipped)
|
|
+ 1
|
|
-------------
|
|
%1111.1100 -4, two's complement</p>
|
|
|
|
<p>Thus, in a single byte, we may represent values in the range</p>
|
|
<p class="explanation-xmp">from -128 (%1000.0000 or $80)
|
|
to +127 (%0111.1111 or $7F)</p>
|
|
<p>A notable feature is that the highest value bit (first bit from the left) will<br />
|
|
always be 1 for a negative value and always be 0 for a positive one, for which<br />
|
|
it is also known as the <em>sign bit</em>. Whenever we interpret a value as a signed<br />
|
|
number, a set sign bit indicates a negative value.<br />
|
|
This works just the same for larger values, e.g., for a signed 16-bit value:</p>
|
|
<p class="explanation-xmp">-512 = %1111.1110.0000.0000 = $FE $00
|
|
-516 = %1111.1101.1111.1100 = $FD $FC (mind how the +1 step carries over)</p>
|
|
<p>Notably, the binary operations are still the same as with unsigned values and<br />
|
|
provide the expected results:<p>
|
|
<p class="explanation-xmp"> <i>dec binary hex</i>
|
|
|
|
100 %0110.0100 $64
|
|
+ -24 %1110.1000 $E8
|
|
------------------------
|
|
76 %0100.1100 $4C (+ carry)</p>
|
|
|
|
<p style="text-indent: -1.25em; padding-left: 1.25em;"><em>Note:</em> We may now see how <code>SBC</code> actually works, by adding <em>ones' complement</em> of<br />
|
|
the operand to the accumulator. If we add 1 from the carry to the result,<br />
|
|
this effectively results in a subtraction in <em>two's complement</em> (the inverse<br />
|
|
of the operand + 1). If the carry happens to be zero, the result falls<br />
|
|
short by 1 in terms of two's complement, which is equivalent to adding 1<br />
|
|
to the operand before the subtraction. Thus, the carry either provides<br />
|
|
the correction required for a valid two's complement representation or,<br />
|
|
if missing, results in a subtraction including a binary borrow.</p>
|
|
|
|
<h3>FLags with ADC and SBC</h3>
|
|
<p>Besides the carry flag (C), which allows us to chain multi-byte operations, the<br />
|
|
CPU sets the following flags on the result of an arithmetic operation:</p>
|
|
<p class="explanation-xmp">zero flag (Z) ........ set if the result is zero, else unset
|
|
negative flag (N) ... the N flag always reflects the sign bit of the result
|
|
overflow flag (V) ... indicates overflow in signed operations</p>
|
|
<p>The latter may require explanation: how is signed overflow different from<br />
|
|
the carry flag? The overflow flag is about a certain ambiguity of the sign bit<br />
|
|
and the negative flag in signed context: if operands are of the same sign, the<br />
|
|
case may occure, where the sign bit flips (as indicated by a change of the<br />
|
|
negative flag), while the result is still of the same sign. This condition is<br />
|
|
indicated by the overflow flag. Notably, such an overflow can never occur, when<br />
|
|
the operands are of opposite signs.</p>
|
|
<p>E.g., adding positive $40 to positive $40:</p>
|
|
<p class="explanation-xmp"><i> acc. acc. flags
|
|
hex binary</i> NVDIZC
|
|
|
|
LDA #$40 $40 %0100.0000 000000
|
|
ADC #$40 $80 %1000.0000 110000</p>
|
|
<p>Here, the change of the sign bit is unrelated to the actual value in the<br />
|
|
accumulator, it is merely a consequence of carry propagation from bit 6 to<br />
|
|
bit 7, the sign bit. Since both operands are positive, the result must be<br />
|
|
positive, as well.<br />
|
|
The overflow flag (V) is of interest in signed context only and has no meaning<br />
|
|
in unsigned context.</p>
|
|
|
|
<h3>Decimal Mode (BCD)</h3>
|
|
<p>Besides binary arithmetic, the 6502 processor supports a second mode, binary<br />
|
|
coded decimal (BCD), where each byte, rather than representing a range of 0…255,<br />
|
|
represents two decimal digits packed into a single byte. For this, a byte is<br />
|
|
thought divided into two sections of 4 bits, the high- and the low-nibble. Only<br />
|
|
values from 0…9 are used for each nibble and a byte can represent a range of a<br />
|
|
2-digit decimal value only, as in 0…99.<br />
|
|
E.g.,</p>
|
|
<p class="explanation-xmp"><i>dec binary hex</i>
|
|
|
|
14 %0001.0100 $14
|
|
98 %1001.1000 $98</p>
|
|
<p>Mind how this intuitively translates to hexadecimal notation, where figures<br />
|
|
A…F are never used.</p>
|
|
<p>Whether or not the processor is in decimal mode is determined by the decimal<br />
|
|
flag (D). If it is set (using <code>SED</code>) the processor will use BCD arithmetic.<br />
|
|
If it is cleared (using <code>CLD</code>), the processor is in binary mode.<br />
|
|
Decimal mode only affects instructions <code>ADC</code> and <code>SBC</code> (but not <code>INC</code> or <code>DEC</code>.)
|
|
<p>Examples:
|
|
<p class="explanation-xmp">SED
|
|
CLC
|
|
LDA #$12
|
|
ADC #$44 ;accumulator now holds $56
|
|
|
|
SED
|
|
CLC
|
|
LDA #$28
|
|
ADC #$14 ;accumulator now holds $42</p>
|
|
<p>Mind that BCD mode is always unsigned:</p>
|
|
<p class="explanation-xmp"> <i>acc.</i> NVDIZC
|
|
SED
|
|
SEC
|
|
LDA #0 $00 001011
|
|
SBC #1 $99 101000</p>
|
|
<p>The carry flag and the zero flag work in decimal mode as expected.<br />
|
|
The negative flag is set similar to binary mode (and of questionable value.)<br />
|
|
The overflow flag has no meaning in decimal mode.</p>
|
|
<p>Multi-byte operations are just as in decimal mode: We first prepare the carry<br />
|
|
and then chain operations of the individual bytes in increasing value order,<br />
|
|
starting with the lowest value pair.</p>
|
|
<p>(It may be important to note that Western Design Center (WDC) version of<br />
|
|
the processor, the 65C02, always clears the decimal flag when it enters an<br />
|
|
interrupt, while the original NMOS version of the 6502 does not.)</p>
|
|
</div>
|
|
|
|
<h2 id="stack">6502 Jump Vectors and Stack Operations</h2>
|
|
<div class="explanation">
|
|
<p>The 256 bytes processor stack of the 6502 is located at $0100 ... $01FF in<br />memory, growing down from top to bottom.</p>
|
|
<p>There are three 2-byte address locations at the very top end of the 64K address<br />space serving as jump vectors for reset/startup and interrupt operations:</p>
|
|
|
|
<p style="margin: 1.5em 0 1.5em 1em;">$FFFA, $FFFB ... NMI (Non-Maskable Interrupt) vector<br />
|
|
$FFFC, $FFFD ... RES (Reset) vector<br />
|
|
$FFFE, $FFFF ... IRQ (Interrupt Request) vector</p>
|
|
|
|
<p>As an interrupt occurs, any instruction currently processed is completed first.<br />
|
|
Only then, the value of the program counter (PC) is put in high-low order onto<br />
|
|
the stack, followed by the value currently in the status register, and control<br />
|
|
will be transferred to the address location found in the respective interrupt<br />
|
|
vector. The registers stored on the stack are recovered at the end of an<br />
|
|
interrupt routine, as control is transferred back to the interrupted code by<br />
|
|
the RTI instruction.</p>
|
|
</div>
|
|
|
|
<figure class="operations">
|
|
<svg x="0px" y="0px" width="470px" height="570px" viewBox="0 0 470 570" enable-background="new 0 0 470 570" role="img" aria-label="6502 Interrupt Operation" style="width: 470px; max-width: 100%; height: auto;">
|
|
<defs>
|
|
<style>
|
|
text
|
|
{
|
|
font-size: 11px;
|
|
font-family: 'm-1m',courier,monospace;
|
|
font-style: normal;
|
|
font-weight: 400;
|
|
line-height: normal;
|
|
text-align: left;
|
|
fill: #000;
|
|
letter-spacing: 0.01em;
|
|
text-shadow: 0 0 1px rgba(0,0,0, 0.25);
|
|
}
|
|
text.caption { font-size: 12px; }
|
|
text.wide { letter-spacing: 0.2em; }
|
|
</style>
|
|
<marker id="arrowhead" viewBox="0 0 12 12" refX="6" refY="6"
|
|
markerWidth="7" markerHeight="7" fill="#000"
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|
orient="auto-start-reverse">
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|
<path d="M 0 1 L 12 5 L 0 11 z" />
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|
</marker>
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<g id="vellip">
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|
<rect x="-1" y="1.5" width="4" height="4.25" fill="#fff" stroke="none" />
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<path stroke="#000" fill="none" d="
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M -5,1.5
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|
q 0,-1.5,3,-1.5
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|
q 3,0,3,1.5
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|
q 0,1.5,3,1.5
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|
q 3,0,3,-1.5" />
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<path stroke="#000" fill="none" stroke-width="0.7" d="
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M -5,6
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q 3,0,3,-1.5" />
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</g>
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<g id="bracket">
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<path stroke="#000" stroke-width="0.5" fill="#000" stroke-miterlimit="10" d="
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M 0,0
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q 0,5,3,6
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q -3,0,-3,6
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q 0,3,0.5,6
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|
q 0,6,-3,6
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|
q 2,0,1,-6
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q 0,-3,-0.5,-6
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q 0,-4,4,-6
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q -4,-2,-4,-6
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q 0,-6,0.5,-6
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q 0.5,-6,-1,-6
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z" />
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</g>
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<g id="basegrid">
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<g stroke="#000">
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<rect x="100" y="1" width="200" height="527" fill="none" />
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<line x1="142" x2="142" y1="21" y2="528" />
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<line x1="184" x2="184" y1="1" y2="528" />
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<line x1="242" x2="242" y1="21" y2="528" />
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<line x1="100" x2="300" y1="21" y2="21" />
|
|
<line x1="100" x2="300" y1="41" y2="41" />
|
|
</g>
|
|
<text x="121" y="16" class="caption">ADDRESS</text>
|
|
<text x="222" y="16" class="caption">MEMORY</text>
|
|
<text x="113" y="36">ADH</text>
|
|
<text x="154" y="36">ADL</text>
|
|
<text x="189" y="36">MNEMONIC</text>
|
|
<text x="251" y="36">OP CODE</text>
|
|
<text x="312" y="36">LOW MEMORY</text>
|
|
<text x="312" y="540">HIGH MEMORY</text>
|
|
<line x1="356" x2="306" y1="41" y2="41" stroke="#000" marker-end="url(#arrowhead)" />
|
|
<line x1="356" x2="306" y1="528" y2="528" stroke="#000" marker-end="url(#arrowhead)" />
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</g>
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</defs>
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<g>
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<rect x="184" y="58" width="59" height="118" fill="#ddd" stroke="none" />
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<rect x="192" y="79" width="38" height="15" fill="#fff" stroke="none" />
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<rect x="201" y="98" width="20" height="15" fill="#fff" stroke="none" />
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</g>
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<path stroke="#000" fill="none" d="
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M 244,57
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q 0,6,6,8
|
|
q -6,0,-6,8
|
|
l 0,12
|
|
q 0,6,-7,6" />
|
|
<text x="107" y="72">0</text><text x="128" y="72">1</text><text x="148" y="72">0</text><text x="169" y="72">E</text>
|
|
<text x="107" y="91">0</text><text x="128" y="91">1</text><text x="148" y="91">0</text><text x="169" y="91">F</text>
|
|
<text x="107" y="110">0</text><text x="128" y="110">1</text><text x="148" y="110">1</text><text x="169" y="110">0</text>
|
|
<text x="107" y="129">0</text><text x="128" y="129">1</text><text x="148" y="129">1</text><text x="169" y="129">1</text>
|
|
<text x="107" y="148">0</text><text x="128" y="148">1</text><text x="148" y="148">1</text><text x="169" y="148">2</text>
|
|
<text x="194" y="91">STATUS</text><text x="267" y="91">•</text>
|
|
<text x="203" y="110"><title>PC Low-Byte</title>PCL</text><text x="265" y="110">02</text>
|
|
<text x="203" y="129"><title>PC High-Byte</title>PCH</text><text x="265" y="129">03</text>
|
|
<text x="259" y="156">STACK</text>
|
|
<use x="100" y="178" xlink:href="#vellip" />
|
|
<use x="142" y="178" xlink:href="#vellip" />
|
|
<use x="182" y="178" xlink:href="#vellip" />
|
|
<use x="242" y="178" xlink:href="#vellip" />
|
|
<use x="300" y="178" xlink:href="#vellip" />
|
|
<text x="107" y="208">0</text><text x="128" y="208">3</text><text x="148" y="208">0</text><text x="169" y="208">0</text>
|
|
<text x="107" y="227">0</text><text x="128" y="227">3</text><text x="148" y="227">0</text><text x="169" y="227">1</text>
|
|
<text x="107" y="246">0</text><text x="128" y="246">3</text><text x="148" y="246">0</text><text x="169" y="246">2</text>
|
|
<text x="107" y="306">0</text><text x="128" y="306">4</text><text x="148" y="306">0</text><text x="169" y="306">5</text><text x="208" y="306">•</text>
|
|
<text x="107" y="325">0</text><text x="128" y="325">4</text><text x="148" y="325">0</text><text x="169" y="325">6</text><text x="208" y="325">•</text>
|
|
<text x="107" y="344">0</text><text x="128" y="344">4</text><text x="148" y="344">0</text><text x="169" y="344">7</text><text x="202" y="344" class="wide">RTI</text><text x="265" y="344">40</text>
|
|
<text x="107" y="426">F</text><text x="128" y="426">F</text><text x="148" y="426">F</text><text x="169" y="426">A</text><text x="202" y="426" class="wide"><title>Address Low-Byte</title>ADL</text>
|
|
<text x="107" y="445">F</text><text x="128" y="445">F</text><text x="148" y="445">F</text><text x="169" y="445">B</text><text x="202" y="445" class="wide"><title>Address High-Byte</title>ADH</text>
|
|
<text x="107" y="464">F</text><text x="128" y="464">F</text><text x="148" y="464">F</text><text x="169" y="464">C</text><text x="202" y="464" class="wide"><title>Address Low-Byte</title>ADL</text>
|
|
<text x="107" y="483">F</text><text x="128" y="483">F</text><text x="148" y="483">F</text><text x="169" y="483">D</text><text x="202" y="483" class="wide"><title>Address High-Byte</title>ADH</text>
|
|
<text x="107" y="502">F</text><text x="128" y="502">F</text><text x="148" y="502">F</text><text x="169" y="502">E</text><text x="202" y="502" class="wide"><title>Address Low-Byte</title>ADL</text><text x="265" y="502">05</text>
|
|
<text x="107" y="521">F</text><text x="128" y="521">F</text><text x="148" y="521">F</text><text x="169" y="521">F</text><text x="202" y="521" class="wide"><title>Address High-Byte</title>ADH</text><text x="265" y="521">04</text>
|
|
<text x="334" y="72">SP AFTER IRQ OR NMI</text><text x="334" y="83">BUT BEFORE RTI</text>
|
|
<text x="334" y="129">SP BEFORE IRQ OR NMI</text><text x="334" y="141">AND AFTER RTI</text>
|
|
<text x="326" y="201">PC AT TIME OF IRQ OR</text><text x="326" y="212">NMI · THIS INSTRUCTION</text><text x="326" y="223">WILL COMPLETE BEFORE</text><text x="326" y="234">INTERRUPT IS SERVICED</text>
|
|
<text x="326" y="246">PC AFTER RTI</text>
|
|
<text x="326" y="306">INTERRUPT SERVICE</text><text x="326" y="318">MAIN BODY</text>
|
|
<text x="326" y="344">RETURN FROM</text><text x="326" y="356">INTERRUPT</text>
|
|
<use x="303" y="414" xlink:href="#bracket" />
|
|
<use x="303" y="452" xlink:href="#bracket" />
|
|
<use x="303" y="490" xlink:href="#bracket" />
|
|
<text x="326" y="436">NMI VECTOR</text>
|
|
<text x="326" y="476">RES VECTOR</text>
|
|
<text x="326" y="512">IRQ VECTOR</text>
|
|
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|
|
<line x1="331" x2="306" y1="125" y2="125" stroke="#000" marker-end="url(#arrowhead)" />
|
|
<line x1="323" x2="306" y1="200" y2="200" stroke="#000" marker-end="url(#arrowhead)" />
|
|
<line x1="323" x2="306" y1="242" y2="242" stroke="#000" marker-end="url(#arrowhead)" />
|
|
<text x="28" y="208" class="wide">PC</text><line x1="44" x2="76" y1="204" y2="204" stroke="#000" marker-end="url(#arrowhead)" />
|
|
<polyline points="100,232,64,232,64,498,95,498" stroke="#000" fill="none" marker-end="url(#arrowhead)" />
|
|
<polyline points="100,517,43,517,43,302,95,302" stroke="#000" fill="none" marker-end="url(#arrowhead)" />
|
|
<polyline points="100,340,1,340,1,242,95,242" stroke="#000" fill="none" marker-end="url(#arrowhead)" />
|
|
<text x="112" y="566" class="caption">IRQ, NMI, RTI, BRK OPERATION</text>
|
|
</svg>
|
|
<figcaption>(Reset after: MCS6502 Instruction Set Summary, MOS Technology, Inc.)</figcaption>
|
|
</figure>
|
|
|
|
<p class="explanation">Similarly, as a JSR instruction is encountered, PC is dumped onto the stack<br />
|
|
and recovered by the JSR instruction. (Here, the value stored is actually the<br />
|
|
address <em>before</em> the location, the program will eventually return to. Thus, the<br />
|
|
effective return address is PC+1.)</p>
|
|
|
|
<figure class="operations">
|
|
<svg x="0px" y="0px" width="470px" height="570px" viewBox="0 0 470 570" enable-background="new 0 0 470 570" role="img" aria-label="6502 Subroutine Operation" style="width: 470px; max-width: 100%; height: auto;">
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</g>
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q 0,6,-7,6" />
|
|
<text x="107" y="72">0</text><text x="128" y="72">1</text><text x="148" y="72">0</text><text x="169" y="72">E</text>
|
|
<text x="107" y="91">0</text><text x="128" y="91">1</text><text x="148" y="91">0</text><text x="169" y="91">F</text>
|
|
<text x="107" y="110">0</text><text x="128" y="110">1</text><text x="148" y="110">1</text><text x="169" y="110">0</text>
|
|
<text x="107" y="129">0</text><text x="128" y="129">1</text><text x="148" y="129">1</text><text x="169" y="129">1</text>
|
|
<text x="203" y="91"><title>PC Low-Byte</title>PCL</text><text x="265" y="91">02</text>
|
|
<text x="203" y="110"><title>PC High-Byte</title>PCH</text><text x="265" y="110">03</text>
|
|
<text x="259" y="132">STACK</text>
|
|
<use x="100" y="158" xlink:href="#vellip" />
|
|
<use x="142" y="158" xlink:href="#vellip" />
|
|
<use x="182" y="158" xlink:href="#vellip" />
|
|
<use x="242" y="158" xlink:href="#vellip" />
|
|
<use x="300" y="158" xlink:href="#vellip" />
|
|
<text x="107" y="188">0</text><text x="128" y="188">3</text><text x="148" y="188">0</text><text x="169" y="188">0</text><text x="202" y="188" class="wide">JSR</text><text x="265" y="188">20</text>
|
|
<text x="107" y="207">0</text><text x="128" y="207">3</text><text x="148" y="207">0</text><text x="169" y="207">1</text><text x="202" y="207" class="wide"><title>Address Low-Byte</title>ADL</text><text x="265" y="207">05</text>
|
|
<text x="107" y="226">0</text><text x="128" y="226">3</text><text x="148" y="226">0</text><text x="169" y="226">2</text><text x="202" y="226" class="wide"><title>Address High-Byte</title>ADH</text><text x="265" y="226">04</text>
|
|
<text x="107" y="245">0</text><text x="128" y="245">3</text><text x="148" y="245">0</text><text x="169" y="245">3</text>
|
|
<use x="100" y="314" xlink:href="#vellip" />
|
|
<use x="142" y="314" xlink:href="#vellip" />
|
|
<use x="182" y="314" xlink:href="#vellip" />
|
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<use x="242" y="314" xlink:href="#vellip" />
|
|
<use x="300" y="314" xlink:href="#vellip" />
|
|
<text x="107" y="346">0</text><text x="128" y="346">4</text><text x="148" y="346">0</text><text x="169" y="346">5</text><text x="208" y="346">•</text>
|
|
<text x="107" y="365">0</text><text x="128" y="365">4</text><text x="148" y="365">0</text><text x="169" y="365">6</text><text x="208" y="365">•</text>
|
|
<text x="107" y="384">0</text><text x="128" y="384">4</text><text x="148" y="384">0</text><text x="169" y="384">7</text><text x="208" y="384">•</text>
|
|
<text x="107" y="403">0</text><text x="128" y="403">4</text><text x="148" y="403">0</text><text x="169" y="403">8</text><text x="202" y="403" class="wide">RTS</text><text x="265" y="403">60</text>
|
|
<text x="334" y="72">SP AFTER JSR BUT BEFORE</text><text x="334" y="83">RETURN (RTS)</text>
|
|
<text x="334" y="110">SP BEFORE JSR AND AFTER</text><text x="334" y="122">RETURN (RTS) FROM</text><text x="334" y="134">SUBROUTINE</text>
|
|
<text x="312" y="188">JUMP TO SUBROUTINE</text>
|
|
<text x="312" y="245">RETURN FROM SUBROUTINE TO</text><text x="312" y="257">THIS LOCATION</text>
|
|
<text x="312" y="346">SUBROUTINE MAIN</text><text x="312" y="358">BODY</text>
|
|
<text x="312" y="403">RETURN FROM SUBROUTINE</text>
|
|
<line x1="331" x2="306" y1="68" y2="68" stroke="#000" stroke-dasharray="3.75 2.5" marker-end="url(#arrowhead)" />
|
|
<line x1="331" x2="306" y1="106" y2="106" stroke="#000" marker-end="url(#arrowhead)" />
|
|
<text x="8" y="184" class="wide">PC</text><line x1="24" x2="56" y1="180" y2="180" stroke="#000" marker-end="url(#arrowhead)" />
|
|
<polyline points="100,184,81,184,81,342,95,342" stroke="#000" fill="none" marker-end="url(#arrowhead)" />
|
|
<polyline points="100,399,62,399,62,241,95,241" stroke="#000" fill="none" marker-end="url(#arrowhead)" />
|
|
<text x="145" y="566" class="caption">JSR, RTS OPERATION</text>
|
|
</svg>
|
|
<figcaption>(Reset after: MCS6502 Instruction Set Summary, MOS Technology, Inc.)</figcaption>
|
|
</figure>
|
|
|
|
<h3 id="interrupt-bugs">Curious Interrupt Behavior</h3>
|
|
<ul class="flaglist">
|
|
<li>If the instruction was a taken branch instruction with 3 cycles execution time (without crossing page boundaries), the interrupt will trigger only after an extra CPU cycle.</li>
|
|
<li>On the NMOS6502, an NMI hardware interrupt occuring at the start of a BRK intruction will hijack the BRK instruction, meanining, the BRK instruction will be executed as normal, but the NMI vector will be used instead of the IRQ vector.</li>
|
|
<li>The 65C02 will clear the decimal flag on any interrupts (and BRK).</li>
|
|
</ul>
|
|
|
|
<h3 id="break-flag">The Break Flag and the Stack</h3>
|
|
<div class="explanation">
|
|
<p>Interrupts and stack operations involving the status register (or P register)<br />
|
|
are the only instances, the break flag appears (namely on the stack).<br />
|
|
It has no representation in the CPU and can't be accessed by any instruction.</p>
|
|
<ul class="flow">
|
|
<li>The break flag will be set to on (1), whenever the transfer was caused by<br />
|
|
software (BRK or PHP).</li>
|
|
<li>The break flag will be set to zero (0), whenever the transfer was caused<br />by a hardware interrupt.</li>
|
|
<li>The break flag will be masked and cleared (0), whenever transferred from<br />
|
|
the stack to the status register, either by PLP or during a return from<br />interrupt (RTI).</li>
|
|
</ul>
|
|
<p>Therefore, it's somewhat difficult to inspect the break flag in order to<br />
|
|
discern a software interrupt (BRK) from a hardware interrupt (NMI or IRQ) and<br />
|
|
the mechanism is seldom used. Accessing a break mark put in the extra byte<br />
|
|
following a BRK instruction is even more cumbersome and probably involves<br />
|
|
indexed zeropage operations.</p>
|
|
<p>Bit 5 (unused) of the status register will be set to 1, whenever the<br />
|
|
register is pushed to the stack. Bits 5 and 4 will always be ignored, when<br />
|
|
transferred to the status register.</p>
|
|
<pre style="margin: 1em 0 2em 0; padding: 0;" class="scp" aria-label="illustrative examples for PHP, PLP, RTI operations">E.g.,
|
|
|
|
<h4 style="margin: 0;" aria-label="example 1: PHP, pushing the status register">1)</h4>
|
|
<span title="status register">SR</span>: <span title="flag labels">N V - B D I Z C</span>
|
|
<span title="flag values">0 0 - - 0 0 1 1</span>
|
|
|
|
PHP <span title="pushes" role="img">-></span> <span title="value on stack">0 0 <strong>1</strong> <strong>1</strong> 0 0 1 1</span> = $33
|
|
|
|
PLP <span title="pulls" role="img"><-</span> <span title="value from stack">0 0 - - 0 0 1 1</span> = $03
|
|
|
|
but:
|
|
|
|
PLA <span title="pulls" role="img"><-</span> <span title="value from stack">0 0 <strong>1</strong> <strong>1</strong> 0 0 1 1</span> = $33
|
|
|
|
|
|
<h4 style="margin: 0;" aria-label="example 2: PLP, pulling the status register">2)</h4>
|
|
LDA #$32 <span title="comment with binary representation">;00110010</span>
|
|
|
|
PHA <span title="pushes" role="img">-></span> <span title="value on stack">0 0 <strong>1</strong> <strong>1</strong> 0 0 1 0</span> = $32
|
|
|
|
PLP <span title="pulls" role="img"><-</span> <span title="value from stack">0 0 - - 0 0 1 0</span> = $02
|
|
|
|
|
|
<h4 style="margin: 0;" title="example 3: RTI">3)</h4>
|
|
LDA #$C0
|
|
PHA <span title="pushes" role="img">-></span> <span title="value on stack">1 1 0 0 0 0 0 0</span> = $C0
|
|
LDA #$08
|
|
PHA <span title="pushes" role="img">-></span> <span title="value on stack">0 0 0 0 1 0 0 0</span> = $08
|
|
LDA #$12
|
|
PHA <span title="pushes" role="img">-></span> <span title="value on stack">0 0 <strong>0</strong> <strong>1</strong> 0 0 1 0</span> = $12
|
|
|
|
RTI
|
|
<span title="resulting processor state">SR: <span title="flag values">0 0 - - 0 0 1 0</span> = $02
|
|
PC: $C008</span></pre>
|
|
|
|
<p>Mind that most emulators are displaying the status register (SR or P) in the<br />state as it would be currently pushed to the stack, with bits 4 and 5 on, adding<br />a bias of $30 to the register value. Here, we chose to rather omit this virtual<br />presence of these bits, since there isn't really a slot for them in the hardware.</p>
|
|
</div>
|
|
|
|
<h2 id="layout">6502 Instruction Layout</h2>
|
|
<div class="explanation">
|
|
<p>The 6502 instruction table is laid out according to a pattern <em>a-b-c,</em> where<br />
|
|
<em>a</em> and <em>b</em> are an octal number each, followed by a group of two binary digits <em>c,</em><br />
|
|
as in the bit-vector <em>"aaabbbcc".</em></p>
|
|
|
|
<table class="instrvector">
|
|
<colgroup>
|
|
<col/>
|
|
<col span="3" class="bits-a"/>
|
|
<col span="3" class="bits-b"/>
|
|
<col span="2" class="bits-c"/>
|
|
</colgroup>
|
|
<tbody>
|
|
<tr><td></td><td class="a">a</td><td class="a">a</td><td class="a">a</td><td class="b">b</td><td class="b">b</td><td class="b">b</td><td class="c">c</td><td class="c">c</td></tr>
|
|
</tbody>
|
|
<tfoot>
|
|
<tr><th scope="row" class="legend">bit</th><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr>
|
|
<tr class="range"><td></td><td colspan="3">(0…7)</td><td colspan="3">(0…7)</td><td colspan="2">(0…3)</td></tr>
|
|
</tfoot>
|
|
</table>
|
|
|
|
<p><u>Example:</u><br />
|
|
All ROR instructions share <em>a</em> = 3 and <em>c</em> = 2 (3<em class="placeholder">b</em>2) with the address mode in <em>b</em>.<br />
|
|
At the same time, all instructions addressing the zero-page share <em>b</em> = 1 (<em class="placeholder">a</em>1<em class="placeholder">c</em>).<br />
|
|
<em>abc</em> = 312 <spa aria-label="transforms to"> =></span> ( 3 <span aria-label="left-shift"><<</span> 5 | 1 <span aria-label="left-shift"><<</span> 2 | 2 ) = %011.001.10 = $66 "ROR zpg".</p>
|
|
|
|
<p>Notably, there are no legal opcodes defined where <em>c</em> = 3, accounting for the<br />
|
|
empty columns in the usual, hexadecimal view of the instruction table.<br />
|
|
(For compactness empty rows where <em>c</em> = 3 are omitted from the tables below.)</p>
|
|
|
|
<p>The following table lists the instruction set, rows sorted by <em>c,</em> then <em>a.</em></p>
|
|
<p>Generally, instructions of a kind are typically found in rows as a combination<br />
|
|
of <em>a</em> and <em>c</em>, and address modes are in columns <em>b</em>.<br />
|
|
However, there are a few exception to this rule, namely, where bits 0 of both<br />
|
|
<em>c</em> and <em>b</em> are low (<em>c</em> = 0, 2; <em>b</em> = 0, 2, 4, 6) and combinations of <em>c</em> and <em>b</em> select<br />
|
|
a group of related operations. (E.g., c=0 ∧ b=4: branch, c=0 ∧ b=6: set flag)</p>
|
|
</div>
|
|
|
|
<div class="instrlayout-wrapper" id="layout-1-1">
|
|
<table class="instrlayout" aria-label="table representing a complex view on the instruction layout according to components a, b, c.">
|
|
<colgroup>
|
|
<col class="bits-c"/>
|
|
<col class="bits-a"/>
|
|
<col span="8" class="bits-b"/>
|
|
</colgroup>
|
|
<thead>
|
|
<tr><th scope="col" rowspan="2">c</th><th rowspan="2" scope="col" title="3 bits">a</th><th colspan="8" scope="colgroup">b</th></tr>
|
|
<tr class="bn b"><th scope="col">0</th><th scope="col">1</th><th scope="col">2</th><th scope="col">3</th><th scope="col">4</th><th scope="col">5</th><th scope="col">6</th><th scope="col">7</th></tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="r1 r-even g-first"><th scope="rowgroup" rowspan="8" class="c c0">0</th><th scope="row" class="a a-b">0</th><td class="v0"><span class="opc">$00</span>BRK impl</td><td class="v1"></td><td class="v2"><span class="opc">$08</span>PHP impl</td><td class="v3"></td><td class="v4"><span class="opc">$10</span>BPL rel</td><td class="v5"></td><td class="v6"><span class="opc">$18</span>CLC impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">1</th><td class="v0"><span class="opc">$20</span>JSR abs</td><td class="v1"><span class="opc">$24</span>BIT zpg</td><td class="v2"><span class="opc">$28</span>PLP impl</td><td class="v3"><span class="opc">$2C</span>BIT abs</td><td class="v4"><span class="opc">$30</span>BMI rel</td><td class="v5"></td><td class="v6"><span class="opc">$38</span>SEC impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">2</th><td class="v0"><span class="opc">$40</span>RTI impl</td><td class="v1"></td><td class="v2"><span class="opc">$48</span>PHA impl</td><td class="v3"><span class="opc">$4C</span>JMP abs</td><td class="v4"><span class="opc">$50</span>BVC rel</td><td class="v5"></td><td class="v6"><span class="opc">$58</span>CLI impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">3</th><td class="v0"><span class="opc">$60</span>RTS impl</td><td class="v1"></td><td class="v2"><span class="opc">$68</span>PLA impl</td><td class="v3"><span class="opc">$6C</span>JMP ind</td><td class="v4"><span class="opc">$70</span>BVS rel</td><td class="v5"></td><td class="v6"><span class="opc">$78</span>SEI impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">4</th><td class="v0"></td><td class="v1"><span class="opc">$84</span>STY zpg</td><td class="v2"><span class="opc">$88</span>DEY impl</td><td class="v3"><span class="opc">$8C</span>STY abs</td><td class="v4"><span class="opc">$90</span>BCC rel</td><td class="v5"><span class="opc">$94</span>STY zpg,X</td><td class="v6"><span class="opc">$98</span>TYA impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">5</th><td class="v0"><span class="opc">$A0</span>LDY #</td><td class="v1"><span class="opc">$A4</span>LDY zpg</td><td class="v2"><span class="opc">$A8</span>TAY impl</td><td class="v3"><span class="opc">$AC</span>LDY abs</td><td class="v4"><span class="opc">$B0</span>BCS rel</td><td class="v5"><span class="opc">$B4</span>LDY zpg,X</td><td class="v6"><span class="opc">$B8</span>CLV impl</td><td class="v7"><span class="opc">$BC</span>LDY abs,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">6</th><td class="v0"><span class="opc">$C0</span>CPY #</td><td class="v1"><span class="opc">$C4</span>CPY zpg</td><td class="v2"><span class="opc">$C8</span>INY impl</td><td class="v3"><span class="opc">$CC</span>CPY abs</td><td class="v4"><span class="opc">$D0</span>BNE rel</td><td class="v5"></td><td class="v6"><span class="opc">$D8</span>CLD impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd g-last"><th scope="row" class="a a-b">7</th><td class="v0"><span class="opc">$E0</span>CPX #</td><td class="v1"><span class="opc">$E4</span>CPX zpg</td><td class="v2"><span class="opc">$E8</span>INX impl</td><td class="v3"><span class="opc">$EC</span>CPX abs</td><td class="v4"><span class="opc">$F0</span>BEQ rel</td><td class="v5"></td><td class="v6"><span class="opc">$F8</span>SED impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-even g-first"><td scope="rowgroup" rowspan="8" class="c c1">1</td><th scope="row" class="a a-b">0</th><td class="v0"><span class="opc">$01</span>ORA X,ind</td><td class="v1"><span class="opc">$05</span>ORA zpg</td><td class="v2"><span class="opc">$09</span>ORA #</td><td class="v3"><span class="opc">$0D</span>ORA abs</td><td class="v4"><span class="opc">$11</span>ORA ind,Y</td><td class="v5"><span class="opc">$15</span>ORA zpg,X</td><td class="v6"><span class="opc">$19</span>ORA abs,Y</td><td class="v7"><span class="opc">$1D</span>ORA abs,X</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">1</th><td class="v0"><span class="opc">$21</span>AND X,ind</td><td class="v1"><span class="opc">$25</span>AND zpg</td><td class="v2"><span class="opc">$29</span>AND #</td><td class="v3"><span class="opc">$2D</span>AND abs</td><td class="v4"><span class="opc">$31</span>AND ind,Y</td><td class="v5"><span class="opc">$35</span>AND zpg,X</td><td class="v6"><span class="opc">$39</span>AND abs,Y</td><td class="v7"><span class="opc">$3D</span>AND abs,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">2</th><td class="v0"><span class="opc">$41</span>EOR X,ind</td><td class="v1"><span class="opc">$45</span>EOR zpg</td><td class="v2"><span class="opc">$49</span>EOR #</td><td class="v3"><span class="opc">$4D</span>EOR abs</td><td class="v4"><span class="opc">$51</span>EOR ind,Y</td><td class="v5"><span class="opc">$55</span>EOR zpg,X</td><td class="v6"><span class="opc">$59</span>EOR abs,Y</td><td class="v7"><span class="opc">$5D</span>EOR abs,X</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">3</th><td class="v0"><span class="opc">$61</span>ADC X,ind</td><td class="v1"><span class="opc">$65</span>ADC zpg</td><td class="v2"><span class="opc">$69</span>ADC #</td><td class="v3"><span class="opc">$6D</span>ADC abs</td><td class="v4"><span class="opc">$71</span>ADC ind,Y</td><td class="v5"><span class="opc">$75</span>ADC zpg,X</td><td class="v6"><span class="opc">$79</span>ADC abs,Y</td><td class="v7"><span class="opc">$7D</span>ADC abs,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">4</th><td class="v0"><span class="opc">$81</span>STA X,ind</td><td class="v1"><span class="opc">$85</span>STA zpg</td><td class="v2"></td><td class="v3"><span class="opc">$8D</span>STA abs</td><td class="v4"><span class="opc">$91</span>STA ind,Y</td><td class="v5"><span class="opc">$95</span>STA zpg,X</td><td class="v6"><span class="opc">$99</span>STA abs,Y</td><td class="v7"><span class="opc">$9D</span>STA abs,X</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">5</th><td class="v0"><span class="opc">$A1</span>LDA X,ind</td><td class="v1"><span class="opc">$A5</span>LDA zpg</td><td class="v2"><span class="opc">$A9</span>LDA #</td><td class="v3"><span class="opc">$AD</span>LDA abs</td><td class="v4"><span class="opc">$B1</span>LDA ind,Y</td><td class="v5"><span class="opc">$B5</span>LDA zpg,X</td><td class="v6"><span class="opc">$B9</span>LDA abs,Y</td><td class="v7"><span class="opc">$BD</span>LDA abs,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">6</th><td class="v0"><span class="opc">$C1</span>CMP X,ind</td><td class="v1"><span class="opc">$C5</span>CMP zpg</td><td class="v2"><span class="opc">$C9</span>CMP #</td><td class="v3"><span class="opc">$CD</span>CMP abs</td><td class="v4"><span class="opc">$D1</span>CMP ind,Y</td><td class="v5"><span class="opc">$D5</span>CMP zpg,X</td><td class="v6"><span class="opc">$D9</span>CMP abs,Y</td><td class="v7"><span class="opc">$DD</span>CMP abs,X</td></tr>
|
|
<tr class="r1 r-odd g-last"><th scope="row" class="a a-b">7</th><td class="v0"><span class="opc">$E1</span>SBC X,ind</td><td class="v1"><span class="opc">$E5</span>SBC zpg</td><td class="v2"><span class="opc">$E9</span>SBC #</td><td class="v3"><span class="opc">$ED</span>SBC abs</td><td class="v4"><span class="opc">$F1</span>SBC ind,Y</td><td class="v5"><span class="opc">$F5</span>SBC zpg,X</td><td class="v6"><span class="opc">$F9</span>SBC abs,Y</td><td class="v7"><span class="opc">$FD</span>SBC abs,X</td></tr>
|
|
<tr class="r1 r-even g-first"><td scope="rowgroup" rowspan="8" class="c c2">2</td><th scope="row" class="a a-b">0</th><td class="v0"></td><td class="v1"><span class="opc">$06</span>ASL zpg</td><td class="v2"><span class="opc">$0A</span>ASL A</td><td class="v3"><span class="opc">$0E</span>ASL abs</td><td class="v4"></td><td class="v5"><span class="opc">$16</span>ASL zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$1E</span>ASL abs,X</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">1</th><td class="v0"></td><td class="v1"><span class="opc">$26</span>ROL zpg</td><td class="v2"><span class="opc">$2A</span>ROL A</td><td class="v3"><span class="opc">$2E</span>ROL abs</td><td class="v4"></td><td class="v5"><span class="opc">$36</span>ROL zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$3E</span>ROL abs,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">2</th><td class="v0"></td><td class="v1"><span class="opc">$46</span>LSR zpg</td><td class="v2"><span class="opc">$4A</span>LSR A</td><td class="v3"><span class="opc">$4E</span>LSR abs</td><td class="v4"></td><td class="v5"><span class="opc">$56</span>LSR zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$5E</span>LSR abs,X</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">3</th><td class="v0"></td><td class="v1"><span class="opc">$66</span>ROR zpg</td><td class="v2"><span class="opc">$6A</span>ROR A</td><td class="v3"><span class="opc">$6E</span>ROR abs</td><td class="v4"></td><td class="v5"><span class="opc">$76</span>ROR zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$7E</span>ROR abs,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">4</th><td class="v0"></td><td class="v1"><span class="opc">$86</span>STX zpg</td><td class="v2"><span class="opc">$8A</span>TXA impl</td><td class="v3"><span class="opc">$8E</span>STX abs</td><td class="v4"></td><td class="v5"><span class="opc">$96</span>STX zpg,Y</td><td class="v6"><span class="opc">$9A</span>TXS impl</td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">5</th><td class="v0"><span class="opc">$A2</span>LDX #</td><td class="v1"><span class="opc">$A6</span>LDX zpg</td><td class="v2"><span class="opc">$AA</span>TAX impl</td><td class="v3"><span class="opc">$AE</span>LDX abs</td><td class="v4"></td><td class="v5"><span class="opc">$B6</span>LDX zpg,Y</td><td class="v6"><span class="opc">$BA</span>TSX impl</td><td class="v7"><span class="opc">$BE</span>LDX abs,Y</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="a a-b">6</th><td class="v0"></td><td class="v1"><span class="opc">$C6</span>DEC zpg</td><td class="v2"><span class="opc">$CA</span>DEX impl</td><td class="v3"><span class="opc">$CE</span>DEC abs</td><td class="v4"></td><td class="v5"><span class="opc">$D6</span>DEC zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$DE</span>DEC abs,X</td></tr>
|
|
<tr class="r1 r-odd g-last"><th scope="row" class="a a-b">7</th><td class="v0"></td><td class="v1"><span class="opc">$E6</span>INC zpg</td><td class="v2"><span class="opc">$EA</span>NOP impl</td><td class="v3"><span class="opc">$EE</span>INC abs</td><td class="v4"></td><td class="v5"><span class="opc">$F6</span>INC zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$FE</span>INC abs,X</td></tr>
|
|
</tbody>
|
|
</table>
|
|
</div>
|
|
<p style="margin: -1.2em 0 2.4em 0;"><em>Note: The operand of instructions like "ASL A" is often depicted as implied, as well.<br />
|
|
Mind that, for any practical reasons, the two notations are interchangeable for any<br />
|
|
instructions involving the accumulator. — However, there are subtle differences.</em></p>
|
|
|
|
<p class="explanation">A rotated view, rows as combinations of <em>c</em> and <em>b,</em> and columns as <em>a</em>:</p>
|
|
|
|
<div class="instrlayout-wrapper" id="layout-1-2">
|
|
<table class="instrlayout" aria-label="table representing a complex view on the instruction layout according to components a, b, c.">
|
|
<colgroup>
|
|
<col class="bits-c"/>
|
|
<col class="bits-b"/>
|
|
<col span="8" class="bits-a"/>
|
|
</colgroup>
|
|
<thead>
|
|
<tr><th scope="col" rowspan="2">c</th><th scope="col" rowspan="2" title="3 bits">b</th><th scope="colgroup" colspan="8">a</th></tr>
|
|
<tr class="bn a"><th scope="col">0</th><th scope="col">1</th><th scope="col">2</th><th scope="col">3</th><th scope="col">4</th><th scope="col">5</th><th scope="col">6</th><th scope="col">7</th></tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="r1 r-even g-first"><th scope="rowgroup" rowspan="8" class="c c0">0</th><th scope="row" class="b a-b">0</th><td class="v0"><span class="opc">$00</span>BRK impl</td><td class="v1"><span class="opc">$20</span>JSR abs</td><td class="v2"><span class="opc">$40</span>RTI impl</td><td class="v3"><span class="opc">$60</span>RTS impl</td><td class="v4"></td><td class="v5"><span class="opc">$A0</span>LDY #</td><td class="v6"><span class="opc">$C0</span>CPY #</td><td class="v7"><span class="opc">$E0</span>CPX #</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">1</th><td class="v0"></td><td class="v1"><span class="opc">$24</span>BIT zpg</td><td class="v2"></td><td class="v3"></td><td class="v4"><span class="opc">$84</span>STY zpg</td><td class="v5"><span class="opc">$A4</span>LDY zpg</td><td class="v6"><span class="opc">$C4</span>CPY zpg</td><td class="v7"><span class="opc">$E4</span>CPX zpg</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">2</th><td class="v0"><span class="opc">$08</span>PHP impl</td><td class="v1"><span class="opc">$28</span>PLP impl</td><td class="v2"><span class="opc">$48</span>PHA impl</td><td class="v3"><span class="opc">$68</span>PLA impl</td><td class="v4"><span class="opc">$88</span>DEY impl</td><td class="v5"><span class="opc">$A8</span>TAY impl</td><td class="v6"><span class="opc">$C8</span>INY impl</td><td class="v7"><span class="opc">$E8</span>INX impl</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">3</th><td class="v0"></td><td class="v1"><span class="opc">$2C</span>BIT abs</td><td class="v2"><span class="opc">$4C</span>JMP abs</td><td class="v3"><span class="opc">$6C</span>JMP ind</td><td class="v4"><span class="opc">$8C</span>STY abs</td><td class="v5"><span class="opc">$AC</span>LDY abs</td><td class="v6"><span class="opc">$CC</span>CPY abs</td><td class="v7"><span class="opc">$EC</span>CPX abs</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">4</th><td class="v0"><span class="opc">$10</span>BPL rel</td><td class="v1"><span class="opc">$30</span>BMI rel</td><td class="v2"><span class="opc">$50</span>BVC rel</td><td class="v3"><span class="opc">$70</span>BVS rel</td><td class="v4"><span class="opc">$90</span>BCC rel</td><td class="v5"><span class="opc">$B0</span>BCS rel</td><td class="v6"><span class="opc">$D0</span>BNE rel</td><td class="v7"><span class="opc">$F0</span>BEQ rel</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">5</th><td class="v0"></td><td class="v1"></td><td class="v2"></td><td class="v3"></td><td class="v4"><span class="opc">$94</span>STY zpg,X</td><td class="v5"><span class="opc">$B4</span>LDY zpg,X</td><td class="v6"></td><td class="v7"></td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">6</th><td class="v0"><span class="opc">$18</span>CLC impl</td><td class="v1"><span class="opc">$38</span>SEC impl</td><td class="v2"><span class="opc">$58</span>CLI impl</td><td class="v3"><span class="opc">$78</span>SEI impl</td><td class="v4"><span class="opc">$98</span>TYA impl</td><td class="v5"><span class="opc">$B8</span>CLV impl</td><td class="v6"><span class="opc">$D8</span>CLD impl</td><td class="v7"><span class="opc">$F8</span>SED impl</td></tr>
|
|
<tr class="r1 r-odd g-last"><th scope="row" class="b a-b">7</th><td class="v0"></td><td class="v1"></td><td class="v2"></td><td class="v3"></td><td class="v4"></td><td class="v5"><span class="opc">$BC</span>LDY abs,X</td><td class="v6"></td><td class="v7"></td></tr>
|
|
<tr class="r1 r-even g-first"><th scope="rowgroup" rowspan="8" class="c c1">1</th><th scope="row" class="b a-b">0</th><td class="v0"><span class="opc">$01</span>ORA X,ind</td><td class="v1"><span class="opc">$21</span>AND X,ind</td><td class="v2"><span class="opc">$41</span>EOR X,ind</td><td class="v3"><span class="opc">$61</span>ADC X,ind</td><td class="v4"><span class="opc">$81</span>STA X,ind</td><td class="v5"><span class="opc">$A1</span>LDA X,ind</td><td class="v6"><span class="opc">$C1</span>CMP X,ind</td><td class="v7"><span class="opc">$E1</span>SBC X,ind</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">1</th><td class="v0"><span class="opc">$05</span>ORA zpg</td><td class="v1"><span class="opc">$25</span>AND zpg</td><td class="v2"><span class="opc">$45</span>EOR zpg</td><td class="v3"><span class="opc">$65</span>ADC zpg</td><td class="v4"><span class="opc">$85</span>STA zpg</td><td class="v5"><span class="opc">$A5</span>LDA zpg</td><td class="v6"><span class="opc">$C5</span>CMP zpg</td><td class="v7"><span class="opc">$E5</span>SBC zpg</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">2</th><td class="v0"><span class="opc">$09</span>ORA #</td><td class="v1"><span class="opc">$29</span>AND #</td><td class="v2"><span class="opc">$49</span>EOR #</td><td class="v3"><span class="opc">$69</span>ADC #</td><td class="v4"></td><td class="v5"><span class="opc">$A9</span>LDA #</td><td class="v6"><span class="opc">$C9</span>CMP #</td><td class="v7"><span class="opc">$E9</span>SBC #</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">3</th><td class="v0"><span class="opc">$0D</span>ORA abs</td><td class="v1"><span class="opc">$2D</span>AND abs</td><td class="v2"><span class="opc">$4D</span>EOR abs</td><td class="v3"><span class="opc">$6D</span>ADC abs</td><td class="v4"><span class="opc">$8D</span>STA abs</td><td class="v5"><span class="opc">$AD</span>LDA abs</td><td class="v6"><span class="opc">$CD</span>CMP abs</td><td class="v7"><span class="opc">$ED</span>SBC abs</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">4</th><td class="v0"><span class="opc">$11</span>ORA ind,Y</td><td class="v1"><span class="opc">$31</span>AND ind,Y</td><td class="v2"><span class="opc">$51</span>EOR ind,Y</td><td class="v3"><span class="opc">$71</span>ADC ind,Y</td><td class="v4"><span class="opc">$91</span>STA ind,Y</td><td class="v5"><span class="opc">$B1</span>LDA ind,Y</td><td class="v6"><span class="opc">$D1</span>CMP ind,Y</td><td class="v7"><span class="opc">$F1</span>SBC ind,Y</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">5</th><td class="v0"><span class="opc">$15</span>ORA zpg,X</td><td class="v1"><span class="opc">$35</span>AND zpg,X</td><td class="v2"><span class="opc">$55</span>EOR zpg,X</td><td class="v3"><span class="opc">$75</span>ADC zpg,X</td><td class="v4"><span class="opc">$95</span>STA zpg,X</td><td class="v5"><span class="opc">$B5</span>LDA zpg,X</td><td class="v6"><span class="opc">$D5</span>CMP zpg,X</td><td class="v7"><span class="opc">$F5</span>SBC zpg,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">6</th><td class="v0"><span class="opc">$19</span>ORA abs,Y</td><td class="v1"><span class="opc">$39</span>AND abs,Y</td><td class="v2"><span class="opc">$59</span>EOR abs,Y</td><td class="v3"><span class="opc">$79</span>ADC abs,Y</td><td class="v4"><span class="opc">$99</span>STA abs,Y</td><td class="v5"><span class="opc">$B9</span>LDA abs,Y</td><td class="v6"><span class="opc">$D9</span>CMP abs,Y</td><td class="v7"><span class="opc">$F9</span>SBC abs,Y</td></tr>
|
|
<tr class="r1 r-odd g-last"><th scope="row" class="b a-b">7</th><td class="v0"><span class="opc">$1D</span>ORA abs,X</td><td class="v1"><span class="opc">$3D</span>AND abs,X</td><td class="v2"><span class="opc">$5D</span>EOR abs,X</td><td class="v3"><span class="opc">$7D</span>ADC abs,X</td><td class="v4"><span class="opc">$9D</span>STA abs,X</td><td class="v5"><span class="opc">$BD</span>LDA abs,X</td><td class="v6"><span class="opc">$DD</span>CMP abs,X</td><td class="v7"><span class="opc">$FD</span>SBC abs,X</td></tr>
|
|
<tr class="r1 r-even g-first"><th scope="rowgroup" rowspan="8" class="c c2">2</th><th scope="row" class="b a-b">0</th><td class="v0"></td><td class="v1"></td><td class="v2"></td><td class="v3"></td><td class="v4"></td><td class="v5"><span class="opc">$A2</span>LDX #</td><td class="v6"></td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">1</th><td class="v0"><span class="opc">$06</span>ASL zpg</td><td class="v1"><span class="opc">$26</span>ROL zpg</td><td class="v2"><span class="opc">$46</span>LSR zpg</td><td class="v3"><span class="opc">$66</span>ROR zpg</td><td class="v4"><span class="opc">$86</span>STX zpg</td><td class="v5"><span class="opc">$A6</span>LDX zpg</td><td class="v6"><span class="opc">$C6</span>DEC zpg</td><td class="v7"><span class="opc">$E6</span>INC zpg</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">2</th><td class="v0"><span class="opc">$0A</span>ASL A</td><td class="v1"><span class="opc">$2A</span>ROL A</td><td class="v2"><span class="opc">$4A</span>LSR A</td><td class="v3"><span class="opc">$6A</span>ROR A</td><td class="v4"><span class="opc">$8A</span>TXA impl</td><td class="v5"><span class="opc">$AA</span>TAX impl</td><td class="v6"><span class="opc">$CA</span>DEX impl</td><td class="v7"><span class="opc">$EA</span>NOP impl</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">3</th><td class="v0"><span class="opc">$0E</span>ASL abs</td><td class="v1"><span class="opc">$2E</span>ROL abs</td><td class="v2"><span class="opc">$4E</span>LSR abs</td><td class="v3"><span class="opc">$6E</span>ROR abs</td><td class="v4"><span class="opc">$8E</span>STX abs</td><td class="v5"><span class="opc">$AE</span>LDX abs</td><td class="v6"><span class="opc">$CE</span>DEC abs</td><td class="v7"><span class="opc">$EE</span>INC abs</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">4</th><td class="v0"></td><td class="v1"></td><td class="v2"></td><td class="v3"></td><td class="v4"></td><td class="v5"></td><td class="v6"></td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="b a-b">5</th><td class="v0"><span class="opc">$16</span>ASL zpg,X</td><td class="v1"><span class="opc">$36</span>ROL zpg,X</td><td class="v2"><span class="opc">$56</span>LSR zpg,X</td><td class="v3"><span class="opc">$76</span>ROR zpg,X</td><td class="v4"><span class="opc">$96</span>STX zpg,Y</td><td class="v5"><span class="opc">$B6</span>LDX zpg,Y</td><td class="v6"><span class="opc">$D6</span>DEC zpg,X</td><td class="v7"><span class="opc">$F6</span>INC zpg,X</td></tr>
|
|
<tr class="r1 r-even"><th scope="row" class="b a-b">6</th><td class="v0"></td><td class="v1"></td><td class="v2"></td><td class="v3"></td><td class="v4"><span class="opc">$9A</span>TXS impl</td><td class="v5"><span class="opc">$BA</span>TSX impl</td><td class="v6"></td><td class="v7"></td></tr>
|
|
<tr class="r1 r-odd g-last"><th scope="row" class="b a-b">7</th><td class="v0"><span class="opc">$1E</span>ASL abs,X</td><td class="v1"><span class="opc">$3E</span>ROL abs,X</td><td class="v2"><span class="opc">$5E</span>LSR abs,X</td><td class="v3"><span class="opc">$7E</span>ROR abs,X</td><td class="v4"></td><td class="v5"><span class="opc">$BE</span>LDX abs,Y</td><td class="v6"><span class="opc">$DE</span>DEC abs,X</td><td class="v7"><span class="opc">$FE</span>INC abs,X</td></tr>
|
|
</tbody>
|
|
</table>
|
|
</div>
|
|
|
|
<div class="explanation">
|
|
<p>Finally, a more complex view, the instruction set listed by rows as<br />
|
|
combinations of <em>a</em> and <em>c,</em> and <em>b</em> in columns:</p>
|
|
<p>Address modes are either a property of <em>b</em> (even columns) or combinations<br />
|
|
of <em>b</em> and <em>c</em> (odd columns with aspecific row-index modulus 3; i.e., every<br />
|
|
third row in a given column). In those latter columns, first and third<br />
|
|
rows (<em>c</em> = 0 and <em>c</em> = 2) refer to the same kind of general operation.</p>
|
|
<p>Load, store and transfer instructions as well as comparisons are typically<br />
|
|
found in the lower half of the table, while most of the arithmetical and<br />
|
|
logical operations as well as stack and jump instructions are found in the<br />
|
|
upper half. (However, mind the exception of SBC as a "mirror" of ADC.)</p>
|
|
</div>
|
|
|
|
<div class="instrlayout-wrapper" id="layout-1-3">
|
|
<table class="instrlayout" aria-label="table representing a complex view on the instruction layout according to components a, b, c.">
|
|
<colgroup>
|
|
<col class="bits-a"/>
|
|
<col class="bits-c"/>
|
|
<col span="8" class="bits-b"/>
|
|
</colgroup>
|
|
<thead>
|
|
<tr><th scope="col" rowspan="2">a</th><th scope="col" rowspan="2" title="2 bits">c</th><th scope="colgroup" colspan="8">b</th></tr>
|
|
<tr class="bn b"><th scope="col">0</th><th scope="col">1</th><th scope="col">2</th><th scope="col">3</th><th scope="col">4</th><th scope="col">5</th><th scope="col">6</th><th scope="col">7</th></tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="r0 g-first r-even"><th scope="rowgroup" rowspan="3" class="a a-b">0</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$00</span>BRK impl</td><td class="v1"></td><td class="v2"><span class="opc">$08</span>PHP impl</td><td class="v3"></td><td class="v4"><span class="opc">$10</span>BPL rel</td><td class="v5"></td><td class="v6"><span class="opc">$18</span>CLC impl</td><td class="v7"></td></tr>
|
|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$01</span>ORA X,ind</td><td class="v1"><span class="opc">$05</span>ORA zpg</td><td class="v2"><span class="opc">$09</span>ORA #</td><td class="v3"><span class="opc">$0D</span>ORA abs</td><td class="v4"><span class="opc">$11</span>ORA ind,Y</td><td class="v5"><span class="opc">$15</span>ORA zpg,X</td><td class="v6"><span class="opc">$19</span>ORA abs,Y</td><td class="v7"><span class="opc">$1D</span>ORA abs,X</td></tr>
|
|
<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0"></td><td class="v1"><span class="opc">$06</span>ASL zpg</td><td class="v2"><span class="opc">$0A</span>ASL A</td><td class="v3"><span class="opc">$0E</span>ASL abs</td><td class="v4"></td><td class="v5"><span class="opc">$16</span>ASL zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$1E</span>ASL abs,X</td></tr>
|
|
<tr class="r0 g-first r-odd"><th scope="rowgroup" rowspan="3" class="a a-b">1</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$20</span>JSR abs</td><td class="v1"><span class="opc">$24</span>BIT zpg</td><td class="v2"><span class="opc">$28</span>PLP impl</td><td class="v3"><span class="opc">$2C</span>BIT abs</td><td class="v4"><span class="opc">$30</span>BMI rel</td><td class="v5"></td><td class="v6"><span class="opc">$38</span>SEC impl</td><td class="v7"></td></tr>
|
|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$21</span>AND X,ind</td><td class="v1"><span class="opc">$25</span>AND zpg</td><td class="v2"><span class="opc">$29</span>AND #</td><td class="v3"><span class="opc">$2D</span>AND abs</td><td class="v4"><span class="opc">$31</span>AND ind,Y</td><td class="v5"><span class="opc">$35</span>AND zpg,X</td><td class="v6"><span class="opc">$39</span>AND abs,Y</td><td class="v7"><span class="opc">$3D</span>AND abs,X</td></tr>
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|
<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0"></td><td class="v1"><span class="opc">$26</span>ROL zpg</td><td class="v2"><span class="opc">$2A</span>ROL A</td><td class="v3"><span class="opc">$2E</span>ROL abs</td><td class="v4"></td><td class="v5"><span class="opc">$36</span>ROL zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$3E</span>ROL abs,X</td></tr>
|
|
<tr class="r0 g-first r-even"><th scope="rowgroup" rowspan="3" class="a a-b">2</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$40</span>RTI impl</td><td class="v1"></td><td class="v2"><span class="opc">$48</span>PHA impl</td><td class="v3"><span class="opc">$4C</span>JMP abs</td><td class="v4"><span class="opc">$50</span>BVC rel</td><td class="v5"></td><td class="v6"><span class="opc">$58</span>CLI impl</td><td class="v7"></td></tr>
|
|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$41</span>EOR X,ind</td><td class="v1"><span class="opc">$45</span>EOR zpg</td><td class="v2"><span class="opc">$49</span>EOR #</td><td class="v3"><span class="opc">$4D</span>EOR abs</td><td class="v4"><span class="opc">$51</span>EOR ind,Y</td><td class="v5"><span class="opc">$55</span>EOR zpg,X</td><td class="v6"><span class="opc">$59</span>EOR abs,Y</td><td class="v7"><span class="opc">$5D</span>EOR abs,X</td></tr>
|
|
<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0"></td><td class="v1"><span class="opc">$46</span>LSR zpg</td><td class="v2"><span class="opc">$4A</span>LSR A</td><td class="v3"><span class="opc">$4E</span>LSR abs</td><td class="v4"></td><td class="v5"><span class="opc">$56</span>LSR zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$5E</span>LSR abs,X</td></tr>
|
|
<tr class="r0 g-first r-odd"><th scope="rowgroup" rowspan="3" class="a a-b">3</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$60</span>RTS impl</td><td class="v1"></td><td class="v2"><span class="opc">$68</span>PLA impl</td><td class="v3"><span class="opc">$6C</span>JMP ind</td><td class="v4"><span class="opc">$70</span>BVS rel</td><td class="v5"></td><td class="v6"><span class="opc">$78</span>SEI impl</td><td class="v7"></td></tr>
|
|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$61</span>ADC X,ind</td><td class="v1"><span class="opc">$65</span>ADC zpg</td><td class="v2"><span class="opc">$69</span>ADC #</td><td class="v3"><span class="opc">$6D</span>ADC abs</td><td class="v4"><span class="opc">$71</span>ADC ind,Y</td><td class="v5"><span class="opc">$75</span>ADC zpg,X</td><td class="v6"><span class="opc">$79</span>ADC abs,Y</td><td class="v7"><span class="opc">$7D</span>ADC abs,X</td></tr>
|
|
<tr class="r2 t-half-top"><th scope="row" class="c c2">2</th><td class="v0"></td><td class="v1"><span class="opc">$66</span>ROR zpg</td><td class="v2"><span class="opc">$6A</span>ROR A</td><td class="v3"><span class="opc">$6E</span>ROR abs</td><td class="v4"></td><td class="v5"><span class="opc">$76</span>ROR zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$7E</span>ROR abs,X</td></tr>
|
|
<tr class="r0 g-first r-even t-half-bottom"><th scope="rowgroup" rowspan="3" class="a a-b">4</th><th scope="row" class="c c0">0</th><td class="v0"></td><td class="v1"><span class="opc">$84</span>STY zpg</td><td class="v2"><span class="opc">$88</span>DEY impl</td><td class="v3"><span class="opc">$8C</span>STY abs</td><td class="v4"><span class="opc">$90</span>BCC rel</td><td class="v5"><span class="opc">$94</span>STY zpg,X</td><td class="v6"><span class="opc">$98</span>TYA impl</td><td class="v7"></td></tr>
|
|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$81</span>STA X,ind</td><td class="v1"><span class="opc">$85</span>STA zpg</td><td class="v2"></td><td class="v3"><span class="opc">$8D</span>STA abs</td><td class="v4"><span class="opc">$91</span>STA ind,Y</td><td class="v5"><span class="opc">$95</span>STA zpg,X</td><td class="v6"><span class="opc">$99</span>STA abs,Y</td><td class="v7"><span class="opc">$9D</span>STA abs,X</td></tr>
|
|
<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0"></td><td class="v1"><span class="opc">$86</span>STX zpg</td><td class="v2"><span class="opc">$8A</span>TXA impl</td><td class="v3"><span class="opc">$8E</span>STX abs</td><td class="v4"></td><td class="v5"><span class="opc">$96</span>STX zpg,Y</td><td class="v6"><span class="opc">$9A</span>TXS impl</td><td class="v7"></td></tr>
|
|
<tr class="r0 g-first r-odd"><th scope="rowgroup" rowspan="3" class="a a-b">5</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$A0</span>LDY #</td><td class="v1"><span class="opc">$A4</span>LDY zpg</td><td class="v2"><span class="opc">$A8</span>TAY impl</td><td class="v3"><span class="opc">$AC</span>LDY abs</td><td class="v4"><span class="opc">$B0</span>BCS rel</td><td class="v5"><span class="opc">$B4</span>LDY zpg,X</td><td class="v6"><span class="opc">$B8</span>CLV impl</td><td class="v7"><span class="opc">$BC</span>LDY abs,X</td></tr>
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|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$A1</span>LDA X,ind</td><td class="v1"><span class="opc">$A5</span>LDA zpg</td><td class="v2"><span class="opc">$A9</span>LDA #</td><td class="v3"><span class="opc">$AD</span>LDA abs</td><td class="v4"><span class="opc">$B1</span>LDA ind,Y</td><td class="v5"><span class="opc">$B5</span>LDA zpg,X</td><td class="v6"><span class="opc">$B9</span>LDA abs,Y</td><td class="v7"><span class="opc">$BD</span>LDA abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0"><span class="opc">$A2</span>LDX #</td><td class="v1"><span class="opc">$A6</span>LDX zpg</td><td class="v2"><span class="opc">$AA</span>TAX impl</td><td class="v3"><span class="opc">$AE</span>LDX abs</td><td class="v4"></td><td class="v5"><span class="opc">$B6</span>LDX zpg,Y</td><td class="v6"><span class="opc">$BA</span>TSX impl</td><td class="v7"><span class="opc">$BE</span>LDX abs,Y</td></tr>
|
|
<tr class="r0 g-first r-even"><th scope="rowgroup" rowspan="3" class="a a-b">6</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$C0</span>CPY #</td><td class="v1"><span class="opc">$C4</span>CPY zpg</td><td class="v2"><span class="opc">$C8</span>INY impl</td><td class="v3"><span class="opc">$CC</span>CPY abs</td><td class="v4"><span class="opc">$D0</span>BNE rel</td><td class="v5"></td><td class="v6"><span class="opc">$D8</span>CLD impl</td><td class="v7"></td></tr>
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|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$C1</span>CMP X,ind</td><td class="v1"><span class="opc">$C5</span>CMP zpg</td><td class="v2"><span class="opc">$C9</span>CMP #</td><td class="v3"><span class="opc">$CD</span>CMP abs</td><td class="v4"><span class="opc">$D1</span>CMP ind,Y</td><td class="v5"><span class="opc">$D5</span>CMP zpg,X</td><td class="v6"><span class="opc">$D9</span>CMP abs,Y</td><td class="v7"><span class="opc">$DD</span>CMP abs,X</td></tr>
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|
<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0"></td><td class="v1"><span class="opc">$C6</span>DEC zpg</td><td class="v2"><span class="opc">$CA</span>DEX impl</td><td class="v3"><span class="opc">$CE</span>DEC abs</td><td class="v4"></td><td class="v5"><span class="opc">$D6</span>DEC zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$DE</span>DEC abs,X</td></tr>
|
|
<tr class="r0 g-first r-odd"><th scope="rowgroup" rowspan="3" class="a a-b">7</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$E0</span>CPX #</td><td class="v1"><span class="opc">$E4</span>CPX zpg</td><td class="v2"><span class="opc">$E8</span>INX impl</td><td class="v3"><span class="opc">$EC</span>CPX abs</td><td class="v4"><span class="opc">$F0</span>BEQ rel</td><td class="v5"></td><td class="v6"><span class="opc">$F8</span>SED impl</td><td class="v7"></td></tr>
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|
<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$E1</span>SBC X,ind</td><td class="v1"><span class="opc">$E5</span>SBC zpg</td><td class="v2"><span class="opc">$E9</span>SBC #</td><td class="v3"><span class="opc">$ED</span>SBC abs</td><td class="v4"><span class="opc">$F1</span>SBC ind,Y</td><td class="v5"><span class="opc">$F5</span>SBC zpg,X</td><td class="v6"><span class="opc">$F9</span>SBC abs,Y</td><td class="v7"><span class="opc">$FD</span>SBC abs,X</td></tr>
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|
<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0"></td><td class="v1"><span class="opc">$E6</span>INC zpg</td><td class="v2"><span class="opc">$EA</span>NOP impl</td><td class="v3"><span class="opc">$EE</span>INC abs</td><td class="v4"></td><td class="v5"><span class="opc">$F6</span>INC zpg,X</td><td class="v6"></td><td class="v7"><span class="opc">$FE</span>INC abs,X</td></tr>
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</tbody>
|
|
</table>
|
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</div>
|
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<h3 style="font-size: 14px;" id="layout-illegals">"Illegal" Opcodes Revisited</h3>
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<p class="explanation">So, how do the "illegal" opcodes fit into this decoding scheme?<br />Let's have a look — "illegals" are shown on grey background.</p>
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|
<p class="explanation">The first view — rows by <em>c</em> and <em>a</em> and columns as <em>b</em> — reveals a strict relation<br />beetween address modes and columns:</p>
|
|
<div class="instrlayout-wrapper" id="layout-2-1">
|
|
<table class="instrlayout" aria-label="table representing a complex view on the instruction layout including illegal opcodes according to components a, b, c.">
|
|
<colgroup>
|
|
<col class="bits-c"/>
|
|
<col class="bits-a"/>
|
|
<col span="8" class="bits-b"/>
|
|
</colgroup>
|
|
<thead>
|
|
<tr><th scope="col" rowspan="2">c</th><th rowspan="2" scope="col" title="3 bits">a</th><th colspan="8" scope="colgroup">b</th></tr>
|
|
<tr class="bn b"><th scope="col">0</th><th scope="col">1</th><th scope="col">2</th><th scope="col">3</th><th scope="col">4</th><th scope="col">5</th><th scope="col">6</th><th scope="col">7</th></tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c0">0</th><th scope="row" class="a a-b">0</th><td class="v0"><span class="opc">$00</span>BRK impl</td><td class="v1 illegal"><span class="opc">$04</span>NOP zpg</td><td class="v2"><span class="opc">$08</span>PHP impl</td><td class="v3 illegal"><span class="opc">$0C</span>NOP abs</td><td class="v4"><span class="opc">$10</span>BPL rel</td><td class="v5 illegal"><span class="opc">$14</span>NOP zpg,X</td><td class="v6"><span class="opc">$18</span>CLC impl</td><td class="v7 illegal"><span class="opc">$1C</span>NOP abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">1</th><td class="v0"><span class="opc">$20</span>JSR abs</td><td class="v1"><span class="opc">$24</span>BIT zpg</td><td class="v2"><span class="opc">$28</span>PLP impl</td><td class="v3"><span class="opc">$2C</span>BIT abs</td><td class="v4"><span class="opc">$30</span>BMI rel</td><td class="v5 illegal"><span class="opc">$34</span>NOP zpg,X</td><td class="v6"><span class="opc">$38</span>SEC impl</td><td class="v7 illegal"><span class="opc">$3C</span>NOP abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">2</th><td class="v0"><span class="opc">$40</span>RTI impl</td><td class="v1 illegal"><span class="opc">$44</span>NOP zpg</td><td class="v2"><span class="opc">$48</span>PHA impl</td><td class="v3"><span class="opc">$4C</span>JMP abs</td><td class="v4"><span class="opc">$50</span>BVC rel</td><td class="v5 illegal"><span class="opc">$54</span>NOP zpg,X</td><td class="v6"><span class="opc">$58</span>CLI impl</td><td class="v7 illegal"><span class="opc">$5C</span>NOP abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">3</th><td class="v0"><span class="opc">$60</span>RTS impl</td><td class="v1 illegal"><span class="opc">$64</span>NOP zpg</td><td class="v2"><span class="opc">$68</span>PLA impl</td><td class="v3"><span class="opc">$6C</span>JMP ind</td><td class="v4"><span class="opc">$70</span>BVS rel</td><td class="v5 illegal"><span class="opc">$74</span>NOP zpg,X</td><td class="v6"><span class="opc">$78</span>SEI impl</td><td class="v7 illegal"><span class="opc">$7C</span>NOP abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">4</th><td class="v0 illegal"><span class="opc">$80</span>NOP #</td><td class="v1"><span class="opc">$84</span>STY zpg</td><td class="v2"><span class="opc">$88</span>DEY impl</td><td class="v3"><span class="opc">$8C</span>STY abs</td><td class="v4"><span class="opc">$90</span>BCC rel</td><td class="v5"><span class="opc">$94</span>STY zpg,X</td><td class="v6"><span class="opc">$98</span>TYA impl</td><td class="v7 illegal"><span class="opc">$9C</span>SHY abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">5</th><td class="v0"><span class="opc">$A0</span>LDY #</td><td class="v1"><span class="opc">$A4</span>LDY zpg</td><td class="v2"><span class="opc">$A8</span>TAY impl</td><td class="v3"><span class="opc">$AC</span>LDY abs</td><td class="v4"><span class="opc">$B0</span>BCS rel</td><td class="v5"><span class="opc">$B4</span>LDY zpg,X</td><td class="v6"><span class="opc">$B8</span>CLV impl</td><td class="v7"><span class="opc">$BC</span>LDY abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">6</th><td class="v0"><span class="opc">$C0</span>CPY #</td><td class="v1"><span class="opc">$C4</span>CPY zpg</td><td class="v2"><span class="opc">$C8</span>INY impl</td><td class="v3"><span class="opc">$CC</span>CPY abs</td><td class="v4"><span class="opc">$D0</span>BNE rel</td><td class="v5 illegal"><span class="opc">$D4</span>NOP zpg,X</td><td class="v6"><span class="opc">$D8</span>CLD impl</td><td class="v7 illegal"><span class="opc">$DC</span>NOP abs,X</td></tr>
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|
<tr class="r1 r-odd g-last"><th scope="row" class="a a-b">7</th><td class="v0"><span class="opc">$E0</span>CPX #</td><td class="v1"><span class="opc">$E4</span>CPX zpg</td><td class="v2"><span class="opc">$E8</span>INX impl</td><td class="v3"><span class="opc">$EC</span>CPX abs</td><td class="v4"><span class="opc">$F0</span>BEQ rel</td><td class="v5 illegal"><span class="opc">$F4</span>NOP zpg,X</td><td class="v6"><span class="opc">$F8</span>SED impl</td><td class="v7 illegal"><span class="opc">$FC</span>NOP abs,X</td></tr>
|
|
<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c1">1</th><th scope="row" class="a a-b">0</th><td class="v0"><span class="opc">$01</span>ORA X,ind</td><td class="v1"><span class="opc">$05</span>ORA zpg</td><td class="v2"><span class="opc">$09</span>ORA #</td><td class="v3"><span class="opc">$0D</span>ORA abs</td><td class="v4"><span class="opc">$11</span>ORA ind,Y</td><td class="v5"><span class="opc">$15</span>ORA zpg,X</td><td class="v6"><span class="opc">$19</span>ORA abs,Y</td><td class="v7"><span class="opc">$1D</span>ORA abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">1</th><td class="v0"><span class="opc">$21</span>AND X,ind</td><td class="v1"><span class="opc">$25</span>AND zpg</td><td class="v2"><span class="opc">$29</span>AND #</td><td class="v3"><span class="opc">$2D</span>AND abs</td><td class="v4"><span class="opc">$31</span>AND ind,Y</td><td class="v5"><span class="opc">$35</span>AND zpg,X</td><td class="v6"><span class="opc">$39</span>AND abs,Y</td><td class="v7"><span class="opc">$3D</span>AND abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">2</th><td class="v0"><span class="opc">$41</span>EOR X,ind</td><td class="v1"><span class="opc">$45</span>EOR zpg</td><td class="v2"><span class="opc">$49</span>EOR #</td><td class="v3"><span class="opc">$4D</span>EOR abs</td><td class="v4"><span class="opc">$51</span>EOR ind,Y</td><td class="v5"><span class="opc">$55</span>EOR zpg,X</td><td class="v6"><span class="opc">$59</span>EOR abs,Y</td><td class="v7"><span class="opc">$5D</span>EOR abs,X</td></tr>
|
|
<tr class="r1 r-odd"><th scope="row" class="a a-b">3</th><td class="v0"><span class="opc">$61</span>ADC X,ind</td><td class="v1"><span class="opc">$65</span>ADC zpg</td><td class="v2"><span class="opc">$69</span>ADC #</td><td class="v3"><span class="opc">$6D</span>ADC abs</td><td class="v4"><span class="opc">$71</span>ADC ind,Y</td><td class="v5"><span class="opc">$75</span>ADC zpg,X</td><td class="v6"><span class="opc">$79</span>ADC abs,Y</td><td class="v7"><span class="opc">$7D</span>ADC abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">4</th><td class="v0"><span class="opc">$81</span>STA X,ind</td><td class="v1"><span class="opc">$85</span>STA zpg</td><td class="v2 illegal"><span class="opc">$89</span>NOP #</td><td class="v3"><span class="opc">$8D</span>STA abs</td><td class="v4"><span class="opc">$91</span>STA ind,Y</td><td class="v5"><span class="opc">$95</span>STA zpg,X</td><td class="v6"><span class="opc">$99</span>STA abs,Y</td><td class="v7"><span class="opc">$9D</span>STA abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">5</th><td class="v0"><span class="opc">$A1</span>LDA X,ind</td><td class="v1"><span class="opc">$A5</span>LDA zpg</td><td class="v2"><span class="opc">$A9</span>LDA #</td><td class="v3"><span class="opc">$AD</span>LDA abs</td><td class="v4"><span class="opc">$B1</span>LDA ind,Y</td><td class="v5"><span class="opc">$B5</span>LDA zpg,X</td><td class="v6"><span class="opc">$B9</span>LDA abs,Y</td><td class="v7"><span class="opc">$BD</span>LDA abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">6</th><td class="v0"><span class="opc">$C1</span>CMP X,ind</td><td class="v1"><span class="opc">$C5</span>CMP zpg</td><td class="v2"><span class="opc">$C9</span>CMP #</td><td class="v3"><span class="opc">$CD</span>CMP abs</td><td class="v4"><span class="opc">$D1</span>CMP ind,Y</td><td class="v5"><span class="opc">$D5</span>CMP zpg,X</td><td class="v6"><span class="opc">$D9</span>CMP abs,Y</td><td class="v7"><span class="opc">$DD</span>CMP abs,X</td></tr>
|
|
<tr class="r1 r-odd g-last"><th scope="row" class="a a-b">7</th><td class="v0"><span class="opc">$E1</span>SBC X,ind</td><td class="v1"><span class="opc">$E5</span>SBC zpg</td><td class="v2"><span class="opc">$E9</span>SBC #</td><td class="v3"><span class="opc">$ED</span>SBC abs</td><td class="v4"><span class="opc">$F1</span>SBC ind,Y</td><td class="v5"><span class="opc">$F5</span>SBC zpg,X</td><td class="v6"><span class="opc">$F9</span>SBC abs,Y</td><td class="v7"><span class="opc">$FD</span>SBC abs,X</td></tr>
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|
<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c2">2</th><th scope="row" class="a a-b">0</th><td class="v0 illegal"><span class="opc">$02</span>JAM </td><td class="v1"><span class="opc">$06</span>ASL zpg</td><td class="v2"><span class="opc">$0A</span>ASL A</td><td class="v3"><span class="opc">$0E</span>ASL abs</td><td class="v4 illegal"><span class="opc">$12</span>JAM </td><td class="v5"><span class="opc">$16</span>ASL zpg,X</td><td class="v6 illegal"><span class="opc">$1A</span>NOP impl</td><td class="v7"><span class="opc">$1E</span>ASL abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">1</th><td class="v0 illegal"><span class="opc">$22</span>JAM </td><td class="v1"><span class="opc">$26</span>ROL zpg</td><td class="v2"><span class="opc">$2A</span>ROL A</td><td class="v3"><span class="opc">$2E</span>ROL abs</td><td class="v4 illegal"><span class="opc">$32</span>JAM </td><td class="v5"><span class="opc">$36</span>ROL zpg,X</td><td class="v6 illegal"><span class="opc">$3A</span>NOP impl</td><td class="v7"><span class="opc">$3E</span>ROL abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">2</th><td class="v0 illegal"><span class="opc">$42</span>JAM </td><td class="v1"><span class="opc">$46</span>LSR zpg</td><td class="v2"><span class="opc">$4A</span>LSR A</td><td class="v3"><span class="opc">$4E</span>LSR abs</td><td class="v4 illegal"><span class="opc">$52</span>JAM </td><td class="v5"><span class="opc">$56</span>LSR zpg,X</td><td class="v6 illegal"><span class="opc">$5A</span>NOP impl</td><td class="v7"><span class="opc">$5E</span>LSR abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">3</th><td class="v0 illegal"><span class="opc">$62</span>JAM </td><td class="v1"><span class="opc">$66</span>ROR zpg</td><td class="v2"><span class="opc">$6A</span>ROR A</td><td class="v3"><span class="opc">$6E</span>ROR abs</td><td class="v4 illegal"><span class="opc">$72</span>JAM </td><td class="v5"><span class="opc">$76</span>ROR zpg,X</td><td class="v6 illegal"><span class="opc">$7A</span>NOP impl</td><td class="v7"><span class="opc">$7E</span>ROR abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">4</th><td class="v0 illegal"><span class="opc">$82</span>NOP #</td><td class="v1"><span class="opc">$86</span>STX zpg</td><td class="v2"><span class="opc">$8A</span>TXA impl</td><td class="v3"><span class="opc">$8E</span>STX abs</td><td class="v4 illegal"><span class="opc">$92</span>JAM </td><td class="v5"><span class="opc">$96</span>STX zpg,Y</td><td class="v6"><span class="opc">$9A</span>TXS impl</td><td class="v7 illegal"><span class="opc">$9E</span>SHX abs,Y</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">5</th><td class="v0"><span class="opc">$A2</span>LDX #</td><td class="v1"><span class="opc">$A6</span>LDX zpg</td><td class="v2"><span class="opc">$AA</span>TAX impl</td><td class="v3"><span class="opc">$AE</span>LDX abs</td><td class="v4 illegal"><span class="opc">$B2</span>JAM </td><td class="v5"><span class="opc">$B6</span>LDX zpg,Y</td><td class="v6"><span class="opc">$BA</span>TSX impl</td><td class="v7"><span class="opc">$BE</span>LDX abs,Y</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">6</th><td class="v0 illegal"><span class="opc">$C2</span>NOP #</td><td class="v1"><span class="opc">$C6</span>DEC zpg</td><td class="v2"><span class="opc">$CA</span>DEX impl</td><td class="v3"><span class="opc">$CE</span>DEC abs</td><td class="v4 illegal"><span class="opc">$D2</span>JAM </td><td class="v5"><span class="opc">$D6</span>DEC zpg,X</td><td class="v6 illegal"><span class="opc">$DA</span>NOP impl</td><td class="v7"><span class="opc">$DE</span>DEC abs,X</td></tr>
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|
<tr class="r1 r-odd g-last"><th scope="row" class="a a-b">7</th><td class="v0 illegal"><span class="opc">$E2</span>NOP #</td><td class="v1"><span class="opc">$E6</span>INC zpg</td><td class="v2"><span class="opc">$EA</span>NOP impl</td><td class="v3"><span class="opc">$EE</span>INC abs</td><td class="v4 illegal"><span class="opc">$F2</span>JAM </td><td class="v5"><span class="opc">$F6</span>INC zpg,X</td><td class="v6 illegal"><span class="opc">$FA</span>NOP impl</td><td class="v7"><span class="opc">$FE</span>INC abs,X</td></tr>
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|
<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c3">3</th><th scope="row" class="a a-b">0</th><td class="v0 illegal"><span class="opc">$03</span>SLO X,ind</td><td class="v1 illegal"><span class="opc">$07</span>SLO zpg</td><td class="v2 illegal"><span class="opc">$0B</span>ANC #</td><td class="v3 illegal"><span class="opc">$0F</span>SLO abs</td><td class="v4 illegal"><span class="opc">$13</span>SLO ind,Y</td><td class="v5 illegal"><span class="opc">$17</span>SLO zpg,X</td><td class="v6 illegal"><span class="opc">$1B</span>SLO abs,Y</td><td class="v7 illegal"><span class="opc">$1F</span>SLO abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">1</th><td class="v0 illegal"><span class="opc">$23</span>RLA X,ind</td><td class="v1 illegal"><span class="opc">$27</span>RLA zpg</td><td class="v2 illegal"><span class="opc">$2B</span>ANC #</td><td class="v3 illegal"><span class="opc">$2F</span>RLA abs</td><td class="v4 illegal"><span class="opc">$33</span>RLA ind,Y</td><td class="v5 illegal"><span class="opc">$37</span>RLA zpg,X</td><td class="v6 illegal"><span class="opc">$3B</span>RLA abs,Y</td><td class="v7 illegal"><span class="opc">$3F</span>RLA abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">2</th><td class="v0 illegal"><span class="opc">$43</span>SRE X,ind</td><td class="v1 illegal"><span class="opc">$47</span>SRE zpg</td><td class="v2 illegal"><span class="opc">$4B</span>ALR #</td><td class="v3 illegal"><span class="opc">$4F</span>SRE abs</td><td class="v4 illegal"><span class="opc">$53</span>SRE ind,Y</td><td class="v5 illegal"><span class="opc">$57</span>SRE zpg,X</td><td class="v6 illegal"><span class="opc">$5B</span>SRE abs,Y</td><td class="v7 illegal"><span class="opc">$5F</span>SRE abs,X</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">3</th><td class="v0 illegal"><span class="opc">$63</span>RRA X,ind</td><td class="v1 illegal"><span class="opc">$67</span>RRA zpg</td><td class="v2 illegal"><span class="opc">$6B</span>ARR #</td><td class="v3 illegal"><span class="opc">$6F</span>RRA abs</td><td class="v4 illegal"><span class="opc">$73</span>RRA ind,Y</td><td class="v5 illegal"><span class="opc">$77</span>RRA zpg,X</td><td class="v6 illegal"><span class="opc">$7B</span>RRA abs,Y</td><td class="v7 illegal"><span class="opc">$7F</span>RRA abs,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="a a-b">4</th><td class="v0 illegal"><span class="opc">$83</span>SAX X,ind</td><td class="v1 illegal"><span class="opc">$87</span>SAX zpg</td><td class="v2 illegal"><span class="opc">$8B</span>ANE #</td><td class="v3 illegal"><span class="opc">$8F</span>SAX abs</td><td class="v4 illegal"><span class="opc">$93</span>SHA ind,Y</td><td class="v5 illegal"><span class="opc">$97</span>SAX zpg,Y</td><td class="v6 illegal"><span class="opc">$9B</span>TAS abs,Y</td><td class="v7 illegal"><span class="opc">$9F</span>SHA abs,Y</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="a a-b">5</th><td class="v0 illegal"><span class="opc">$A3</span>LAX X,ind</td><td class="v1 illegal"><span class="opc">$A7</span>LAX zpg</td><td class="v2 illegal"><span class="opc">$AB</span>LXA #</td><td class="v3 illegal"><span class="opc">$AF</span>LAX abs</td><td class="v4 illegal"><span class="opc">$B3</span>LAX ind,Y</td><td class="v5 illegal"><span class="opc">$B7</span>LAX zpg,Y</td><td class="v6 illegal"><span class="opc">$BB</span>LAS abs,Y</td><td class="v7 illegal"><span class="opc">$BF</span>LAX abs,Y</td></tr>
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<tr class="r1 r-even"><th scope="row" class="a a-b">6</th><td class="v0 illegal"><span class="opc">$C3</span>DCP X,ind</td><td class="v1 illegal"><span class="opc">$C7</span>DCP zpg</td><td class="v2 illegal"><span class="opc">$CB</span>SBX #</td><td class="v3 illegal"><span class="opc">$CF</span>DCP abs</td><td class="v4 illegal"><span class="opc">$D3</span>DCP ind,Y</td><td class="v5 illegal"><span class="opc">$D7</span>DCP zpg,X</td><td class="v6 illegal"><span class="opc">$DB</span>DCP abs,Y</td><td class="v7 illegal"><span class="opc">$DF</span>DCP abs,X</td></tr>
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|
<tr class="r1 r-odd g-last"><th scope="row" class="a a-b">7</th><td class="v0 illegal"><span class="opc">$E3</span>ISC X,ind</td><td class="v1 illegal"><span class="opc">$E7</span>ISC zpg</td><td class="v2 illegal"><span class="opc">$EB</span>USBC #</td><td class="v3 illegal"><span class="opc">$EF</span>ISC abs</td><td class="v4 illegal"><span class="opc">$F3</span>ISC ind,Y</td><td class="v5 illegal"><span class="opc">$F7</span>ISC zpg,X</td><td class="v6 illegal"><span class="opc">$FB</span>ISC abs,Y</td><td class="v7 illegal"><span class="opc">$FF</span>ISC abs,X</td></tr>
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</tbody>
|
|
</table>
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</div>
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<p class="explanation">And, again, as a rotated view, rows as combinations of <em>c</em> and <em>b,</em> and columns as <em>a</em>.<br />We may observe a close relationship between the legal and the undocumented<br />instructions in the vertical (quarter-)segements of each column.</p>
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<div class="instrlayout-wrapper" id="layout-2-2">
|
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<table class="instrlayout" aria-label="table representing a complex view on the instruction layout including illegal opcodes according to components a, b, c.">
|
|
<colgroup>
|
|
<col class="bits-c"/>
|
|
<col class="bits-b"/>
|
|
<col span="8" class="bits-a"/>
|
|
</colgroup>
|
|
<thead>
|
|
<tr><th scope="col" rowspan="2">c</th><th scope="col" rowspan="2" title="3 bits">b</th><th scope="colgroup" colspan="8">a</th></tr>
|
|
<tr class="bn a"><th scope="col">0</th><th scope="col">1</th><th scope="col">2</th><th scope="col">3</th><th scope="col">4</th><th scope="col">5</th><th scope="col">6</th><th scope="col">7</th></tr>
|
|
</thead>
|
|
<tbody>
|
|
<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c0">0</th><th scope="row" class="b a-b">0</th><td class="v0"><span class="opc">$00</span>BRK impl</td><td class="v1"><span class="opc">$20</span>JSR abs</td><td class="v2"><span class="opc">$40</span>RTI impl</td><td class="v3"><span class="opc">$60</span>RTS impl</td><td class="v4 illegal"><span class="opc">$80</span>NOP #</td><td class="v5"><span class="opc">$A0</span>LDY #</td><td class="v6"><span class="opc">$C0</span>CPY #</td><td class="v7"><span class="opc">$E0</span>CPX #</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">1</th><td class="v0 illegal"><span class="opc">$04</span>NOP zpg</td><td class="v1"><span class="opc">$24</span>BIT zpg</td><td class="v2 illegal"><span class="opc">$44</span>NOP zpg</td><td class="v3 illegal"><span class="opc">$64</span>NOP zpg</td><td class="v4"><span class="opc">$84</span>STY zpg</td><td class="v5"><span class="opc">$A4</span>LDY zpg</td><td class="v6"><span class="opc">$C4</span>CPY zpg</td><td class="v7"><span class="opc">$E4</span>CPX zpg</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="b a-b">2</th><td class="v0"><span class="opc">$08</span>PHP impl</td><td class="v1"><span class="opc">$28</span>PLP impl</td><td class="v2"><span class="opc">$48</span>PHA impl</td><td class="v3"><span class="opc">$68</span>PLA impl</td><td class="v4"><span class="opc">$88</span>DEY impl</td><td class="v5"><span class="opc">$A8</span>TAY impl</td><td class="v6"><span class="opc">$C8</span>INY impl</td><td class="v7"><span class="opc">$E8</span>INX impl</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="b a-b">3</th><td class="v0 illegal"><span class="opc">$0C</span>NOP abs</td><td class="v1"><span class="opc">$2C</span>BIT abs</td><td class="v2"><span class="opc">$4C</span>JMP abs</td><td class="v3"><span class="opc">$6C</span>JMP ind</td><td class="v4"><span class="opc">$8C</span>STY abs</td><td class="v5"><span class="opc">$AC</span>LDY abs</td><td class="v6"><span class="opc">$CC</span>CPY abs</td><td class="v7"><span class="opc">$EC</span>CPX abs</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="b a-b">4</th><td class="v0"><span class="opc">$10</span>BPL rel</td><td class="v1"><span class="opc">$30</span>BMI rel</td><td class="v2"><span class="opc">$50</span>BVC rel</td><td class="v3"><span class="opc">$70</span>BVS rel</td><td class="v4"><span class="opc">$90</span>BCC rel</td><td class="v5"><span class="opc">$B0</span>BCS rel</td><td class="v6"><span class="opc">$D0</span>BNE rel</td><td class="v7"><span class="opc">$F0</span>BEQ rel</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">5</th><td class="v0 illegal"><span class="opc">$14</span>NOP zpg,X</td><td class="v1 illegal"><span class="opc">$34</span>NOP zpg,X</td><td class="v2 illegal"><span class="opc">$54</span>NOP zpg,X</td><td class="v3 illegal"><span class="opc">$74</span>NOP zpg,X</td><td class="v4"><span class="opc">$94</span>STY zpg,X</td><td class="v5"><span class="opc">$B4</span>LDY zpg,X</td><td class="v6 illegal"><span class="opc">$D4</span>NOP zpg,X</td><td class="v7 illegal"><span class="opc">$F4</span>NOP zpg,X</td></tr>
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<tr class="r1 r-even"><th scope="row" class="b a-b">6</th><td class="v0"><span class="opc">$18</span>CLC impl</td><td class="v1"><span class="opc">$38</span>SEC impl</td><td class="v2"><span class="opc">$58</span>CLI impl</td><td class="v3"><span class="opc">$78</span>SEI impl</td><td class="v4"><span class="opc">$98</span>TYA impl</td><td class="v5"><span class="opc">$B8</span>CLV impl</td><td class="v6"><span class="opc">$D8</span>CLD impl</td><td class="v7"><span class="opc">$F8</span>SED impl</td></tr>
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<tr class="r1 r-odd g-last"><th scope="row" class="b a-b">7</th><td class="v0 illegal"><span class="opc">$1C</span>NOP abs,X</td><td class="v1 illegal"><span class="opc">$3C</span>NOP abs,X</td><td class="v2 illegal"><span class="opc">$5C</span>NOP abs,X</td><td class="v3 illegal"><span class="opc">$7C</span>NOP abs,X</td><td class="v4 illegal"><span class="opc">$9C</span>SHY abs,X</td><td class="v5"><span class="opc">$BC</span>LDY abs,X</td><td class="v6 illegal"><span class="opc">$DC</span>NOP abs,X</td><td class="v7 illegal"><span class="opc">$FC</span>NOP abs,X</td></tr>
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<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c1">1</th><th scope="row" class="b a-b">0</th><td class="v0"><span class="opc">$01</span>ORA X,ind</td><td class="v1"><span class="opc">$21</span>AND X,ind</td><td class="v2"><span class="opc">$41</span>EOR X,ind</td><td class="v3"><span class="opc">$61</span>ADC X,ind</td><td class="v4"><span class="opc">$81</span>STA X,ind</td><td class="v5"><span class="opc">$A1</span>LDA X,ind</td><td class="v6"><span class="opc">$C1</span>CMP X,ind</td><td class="v7"><span class="opc">$E1</span>SBC X,ind</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">1</th><td class="v0"><span class="opc">$05</span>ORA zpg</td><td class="v1"><span class="opc">$25</span>AND zpg</td><td class="v2"><span class="opc">$45</span>EOR zpg</td><td class="v3"><span class="opc">$65</span>ADC zpg</td><td class="v4"><span class="opc">$85</span>STA zpg</td><td class="v5"><span class="opc">$A5</span>LDA zpg</td><td class="v6"><span class="opc">$C5</span>CMP zpg</td><td class="v7"><span class="opc">$E5</span>SBC zpg</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="b a-b">2</th><td class="v0"><span class="opc">$09</span>ORA #</td><td class="v1"><span class="opc">$29</span>AND #</td><td class="v2"><span class="opc">$49</span>EOR #</td><td class="v3"><span class="opc">$69</span>ADC #</td><td class="v4 illegal"><span class="opc">$89</span>NOP #</td><td class="v5"><span class="opc">$A9</span>LDA #</td><td class="v6"><span class="opc">$C9</span>CMP #</td><td class="v7"><span class="opc">$E9</span>SBC #</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">3</th><td class="v0"><span class="opc">$0D</span>ORA abs</td><td class="v1"><span class="opc">$2D</span>AND abs</td><td class="v2"><span class="opc">$4D</span>EOR abs</td><td class="v3"><span class="opc">$6D</span>ADC abs</td><td class="v4"><span class="opc">$8D</span>STA abs</td><td class="v5"><span class="opc">$AD</span>LDA abs</td><td class="v6"><span class="opc">$CD</span>CMP abs</td><td class="v7"><span class="opc">$ED</span>SBC abs</td></tr>
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<tr class="r1 r-even"><th scope="row" class="b a-b">4</th><td class="v0"><span class="opc">$11</span>ORA ind,Y</td><td class="v1"><span class="opc">$31</span>AND ind,Y</td><td class="v2"><span class="opc">$51</span>EOR ind,Y</td><td class="v3"><span class="opc">$71</span>ADC ind,Y</td><td class="v4"><span class="opc">$91</span>STA ind,Y</td><td class="v5"><span class="opc">$B1</span>LDA ind,Y</td><td class="v6"><span class="opc">$D1</span>CMP ind,Y</td><td class="v7"><span class="opc">$F1</span>SBC ind,Y</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">5</th><td class="v0"><span class="opc">$15</span>ORA zpg,X</td><td class="v1"><span class="opc">$35</span>AND zpg,X</td><td class="v2"><span class="opc">$55</span>EOR zpg,X</td><td class="v3"><span class="opc">$75</span>ADC zpg,X</td><td class="v4"><span class="opc">$95</span>STA zpg,X</td><td class="v5"><span class="opc">$B5</span>LDA zpg,X</td><td class="v6"><span class="opc">$D5</span>CMP zpg,X</td><td class="v7"><span class="opc">$F5</span>SBC zpg,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="b a-b">6</th><td class="v0"><span class="opc">$19</span>ORA abs,Y</td><td class="v1"><span class="opc">$39</span>AND abs,Y</td><td class="v2"><span class="opc">$59</span>EOR abs,Y</td><td class="v3"><span class="opc">$79</span>ADC abs,Y</td><td class="v4"><span class="opc">$99</span>STA abs,Y</td><td class="v5"><span class="opc">$B9</span>LDA abs,Y</td><td class="v6"><span class="opc">$D9</span>CMP abs,Y</td><td class="v7"><span class="opc">$F9</span>SBC abs,Y</td></tr>
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<tr class="r1 r-odd g-last"><th scope="row" class="b a-b">7</th><td class="v0"><span class="opc">$1D</span>ORA abs,X</td><td class="v1"><span class="opc">$3D</span>AND abs,X</td><td class="v2"><span class="opc">$5D</span>EOR abs,X</td><td class="v3"><span class="opc">$7D</span>ADC abs,X</td><td class="v4"><span class="opc">$9D</span>STA abs,X</td><td class="v5"><span class="opc">$BD</span>LDA abs,X</td><td class="v6"><span class="opc">$DD</span>CMP abs,X</td><td class="v7"><span class="opc">$FD</span>SBC abs,X</td></tr>
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<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c2">2</th><th scope="row" class="b a-b">0</th><td class="v0 illegal"><span class="opc">$02</span>JAM </td><td class="v1 illegal"><span class="opc">$22</span>JAM </td><td class="v2 illegal"><span class="opc">$42</span>JAM </td><td class="v3 illegal"><span class="opc">$62</span>JAM </td><td class="v4 illegal"><span class="opc">$82</span>NOP #</td><td class="v5"><span class="opc">$A2</span>LDX #</td><td class="v6 illegal"><span class="opc">$C2</span>NOP #</td><td class="v7 illegal"><span class="opc">$E2</span>NOP #</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">1</th><td class="v0"><span class="opc">$06</span>ASL zpg</td><td class="v1"><span class="opc">$26</span>ROL zpg</td><td class="v2"><span class="opc">$46</span>LSR zpg</td><td class="v3"><span class="opc">$66</span>ROR zpg</td><td class="v4"><span class="opc">$86</span>STX zpg</td><td class="v5"><span class="opc">$A6</span>LDX zpg</td><td class="v6"><span class="opc">$C6</span>DEC zpg</td><td class="v7"><span class="opc">$E6</span>INC zpg</td></tr>
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<tr class="r1 r-even"><th scope="row" class="b a-b">2</th><td class="v0"><span class="opc">$0A</span>ASL A</td><td class="v1"><span class="opc">$2A</span>ROL A</td><td class="v2"><span class="opc">$4A</span>LSR A</td><td class="v3"><span class="opc">$6A</span>ROR A</td><td class="v4"><span class="opc">$8A</span>TXA impl</td><td class="v5"><span class="opc">$AA</span>TAX impl</td><td class="v6"><span class="opc">$CA</span>DEX impl</td><td class="v7"><span class="opc">$EA</span>NOP impl</td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="b a-b">3</th><td class="v0"><span class="opc">$0E</span>ASL abs</td><td class="v1"><span class="opc">$2E</span>ROL abs</td><td class="v2"><span class="opc">$4E</span>LSR abs</td><td class="v3"><span class="opc">$6E</span>ROR abs</td><td class="v4"><span class="opc">$8E</span>STX abs</td><td class="v5"><span class="opc">$AE</span>LDX abs</td><td class="v6"><span class="opc">$CE</span>DEC abs</td><td class="v7"><span class="opc">$EE</span>INC abs</td></tr>
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<tr class="r1 r-even"><th scope="row" class="b a-b">4</th><td class="v0 illegal"><span class="opc">$12</span>JAM </td><td class="v1 illegal"><span class="opc">$32</span>JAM </td><td class="v2 illegal"><span class="opc">$52</span>JAM </td><td class="v3 illegal"><span class="opc">$72</span>JAM </td><td class="v4 illegal"><span class="opc">$92</span>JAM </td><td class="v5 illegal"><span class="opc">$B2</span>JAM </td><td class="v6 illegal"><span class="opc">$D2</span>JAM </td><td class="v7 illegal"><span class="opc">$F2</span>JAM </td></tr>
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|
<tr class="r1 r-odd"><th scope="row" class="b a-b">5</th><td class="v0"><span class="opc">$16</span>ASL zpg,X</td><td class="v1"><span class="opc">$36</span>ROL zpg,X</td><td class="v2"><span class="opc">$56</span>LSR zpg,X</td><td class="v3"><span class="opc">$76</span>ROR zpg,X</td><td class="v4"><span class="opc">$96</span>STX zpg,Y</td><td class="v5"><span class="opc">$B6</span>LDX zpg,Y</td><td class="v6"><span class="opc">$D6</span>DEC zpg,X</td><td class="v7"><span class="opc">$F6</span>INC zpg,X</td></tr>
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|
<tr class="r1 r-even"><th scope="row" class="b a-b">6</th><td class="v0 illegal"><span class="opc">$1A</span>NOP impl</td><td class="v1 illegal"><span class="opc">$3A</span>NOP impl</td><td class="v2 illegal"><span class="opc">$5A</span>NOP impl</td><td class="v3 illegal"><span class="opc">$7A</span>NOP impl</td><td class="v4"><span class="opc">$9A</span>TXS impl</td><td class="v5"><span class="opc">$BA</span>TSX impl</td><td class="v6 illegal"><span class="opc">$DA</span>NOP impl</td><td class="v7 illegal"><span class="opc">$FA</span>NOP impl</td></tr>
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|
<tr class="r1 r-odd g-last"><th scope="row" class="b a-b">7</th><td class="v0"><span class="opc">$1E</span>ASL abs,X</td><td class="v1"><span class="opc">$3E</span>ROL abs,X</td><td class="v2"><span class="opc">$5E</span>LSR abs,X</td><td class="v3"><span class="opc">$7E</span>ROR abs,X</td><td class="v4 illegal"><span class="opc">$9E</span>SHX abs,Y</td><td class="v5"><span class="opc">$BE</span>LDX abs,Y</td><td class="v6"><span class="opc">$DE</span>DEC abs,X</td><td class="v7"><span class="opc">$FE</span>INC abs,X</td></tr>
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<tr class="r1 r-even g-first"><th rowspan="8" scope="rowgroup" class="c c3">3</th><th scope="row" class="b a-b">0</th><td class="v0 illegal"><span class="opc">$03</span>SLO X,ind</td><td class="v1 illegal"><span class="opc">$23</span>RLA X,ind</td><td class="v2 illegal"><span class="opc">$43</span>SRE X,ind</td><td class="v3 illegal"><span class="opc">$63</span>RRA X,ind</td><td class="v4 illegal"><span class="opc">$83</span>SAX X,ind</td><td class="v5 illegal"><span class="opc">$A3</span>LAX X,ind</td><td class="v6 illegal"><span class="opc">$C3</span>DCP X,ind</td><td class="v7 illegal"><span class="opc">$E3</span>ISC X,ind</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">1</th><td class="v0 illegal"><span class="opc">$07</span>SLO zpg</td><td class="v1 illegal"><span class="opc">$27</span>RLA zpg</td><td class="v2 illegal"><span class="opc">$47</span>SRE zpg</td><td class="v3 illegal"><span class="opc">$67</span>RRA zpg</td><td class="v4 illegal"><span class="opc">$87</span>SAX zpg</td><td class="v5 illegal"><span class="opc">$A7</span>LAX zpg</td><td class="v6 illegal"><span class="opc">$C7</span>DCP zpg</td><td class="v7 illegal"><span class="opc">$E7</span>ISC zpg</td></tr>
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<tr class="r1 r-even"><th scope="row" class="b a-b">2</th><td class="v0 illegal"><span class="opc">$0B</span>ANC #</td><td class="v1 illegal"><span class="opc">$2B</span>ANC #</td><td class="v2 illegal"><span class="opc">$4B</span>ALR #</td><td class="v3 illegal"><span class="opc">$6B</span>ARR #</td><td class="v4 illegal"><span class="opc">$8B</span>ANE #</td><td class="v5 illegal"><span class="opc">$AB</span>LXA #</td><td class="v6 illegal"><span class="opc">$CB</span>SBX #</td><td class="v7 illegal"><span class="opc">$EB</span>USBC #</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">3</th><td class="v0 illegal"><span class="opc">$0F</span>SLO abs</td><td class="v1 illegal"><span class="opc">$2F</span>RLA abs</td><td class="v2 illegal"><span class="opc">$4F</span>SRE abs</td><td class="v3 illegal"><span class="opc">$6F</span>RRA abs</td><td class="v4 illegal"><span class="opc">$8F</span>SAX abs</td><td class="v5 illegal"><span class="opc">$AF</span>LAX abs</td><td class="v6 illegal"><span class="opc">$CF</span>DCP abs</td><td class="v7 illegal"><span class="opc">$EF</span>ISC abs</td></tr>
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<tr class="r1 r-even"><th scope="row" class="b a-b">4</th><td class="v0 illegal"><span class="opc">$13</span>SLO ind,Y</td><td class="v1 illegal"><span class="opc">$33</span>RLA ind,Y</td><td class="v2 illegal"><span class="opc">$53</span>SRE ind,Y</td><td class="v3 illegal"><span class="opc">$73</span>RRA ind,Y</td><td class="v4 illegal"><span class="opc">$93</span>SHA ind,Y</td><td class="v5 illegal"><span class="opc">$B3</span>LAX ind,Y</td><td class="v6 illegal"><span class="opc">$D3</span>DCP ind,Y</td><td class="v7 illegal"><span class="opc">$F3</span>ISC ind,Y</td></tr>
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<tr class="r1 r-odd"><th scope="row" class="b a-b">5</th><td class="v0 illegal"><span class="opc">$17</span>SLO zpg,X</td><td class="v1 illegal"><span class="opc">$37</span>RLA zpg,X</td><td class="v2 illegal"><span class="opc">$57</span>SRE zpg,X</td><td class="v3 illegal"><span class="opc">$77</span>RRA zpg,X</td><td class="v4 illegal"><span class="opc">$97</span>SAX zpg,Y</td><td class="v5 illegal"><span class="opc">$B7</span>LAX zpg,Y</td><td class="v6 illegal"><span class="opc">$D7</span>DCP zpg,X</td><td class="v7 illegal"><span class="opc">$F7</span>ISC zpg,X</td></tr>
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<tr class="r1 r-even"><th scope="row" class="b a-b">6</th><td class="v0 illegal"><span class="opc">$1B</span>SLO abs,Y</td><td class="v1 illegal"><span class="opc">$3B</span>RLA abs,Y</td><td class="v2 illegal"><span class="opc">$5B</span>SRE abs,Y</td><td class="v3 illegal"><span class="opc">$7B</span>RRA abs,Y</td><td class="v4 illegal"><span class="opc">$9B</span>TAS abs,Y</td><td class="v5 illegal"><span class="opc">$BB</span>LAS abs,Y</td><td class="v6 illegal"><span class="opc">$DB</span>DCP abs,Y</td><td class="v7 illegal"><span class="opc">$FB</span>ISC abs,Y</td></tr>
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<tr class="r1 r-odd g-last"><th scope="row" class="b a-b">7</th><td class="v0 illegal"><span class="opc">$1F</span>SLO abs,X</td><td class="v1 illegal"><span class="opc">$3F</span>RLA abs,X</td><td class="v2 illegal"><span class="opc">$5F</span>SRE abs,X</td><td class="v3 illegal"><span class="opc">$7F</span>RRA abs,X</td><td class="v4 illegal"><span class="opc">$9F</span>SHA abs,Y</td><td class="v5 illegal"><span class="opc">$BF</span>LAX abs,Y</td><td class="v6 illegal"><span class="opc">$DF</span>DCP abs,X</td><td class="v7 illegal"><span class="opc">$FF</span>ISC abs,X</td></tr>
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</tbody>
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</table>
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</div>
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<p class="explanation">And, finally, in a third view, we may observe how each of the rows of "illegal"<br />instructions at <em>c = 3</em> inherits behavior from the two rows with <em>c = 1</em> and <em>c = 2</em><br />immediately above, combining the operations of these instructions with the<br /> address mode of the respective instruction at <em>c = 1</em>.<br />(Mind that in binary 3 is the combination of 2 and 1, bits 0 and 1 both set.)</p>
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<p class="explanation">We may further observe that additional NOPs result from non-effective or non-<br />sensical combinations of operations and address modes, e.g., instr. $89, which<br />would be "STA #", storing the contents of the accumulator in the operand.<br />Some other instructions, typically combinations involving indirect indexed<br />addressing, fail over unresolved timing issues entirely, resulting in a "JAM".</p>
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<p class="explanation">(We me also observe that there is indeed a difference in accumulator mode<br />— as in "OPC A" — and immediate addressing. E.g., $6A, "ROR A", is a valid<br />instruction, while instruction $7A, "ROR implied", is a NOP.<br />We may also note how "ROR X,ind" at $62 and "ROR ind,Y" at $72 fail entirely<br /> and result in a JAM.)</p>
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<div class="instrlayout-wrapper" id="layout-2-3">
|
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<table class="instrlayout" aria-label="table representing a complex view on the instruction layout including illegal opcodes according to components a, c, b.">
|
|
<colgroup>
|
|
<col class="bits-a"/>
|
|
<col class="bits-c"/>
|
|
<col span="8" class="bits-b"/>
|
|
</colgroup>
|
|
<thead>
|
|
<tr><th scope="col" rowspan="2">a</th><th scope="col" rowspan="2" title="2 bits">c</th><th scope="colgroup" colspan="8">b</th></tr>
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<tr class="bn b0"><th scope="col">0</th><th scope="col">1</th><th scope="col">2</th><th scope="col">3</th><th scope="col">4</th><th scope="col">5</th><th scope="col">6</th><th scope="col">7</th></tr>
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</thead>
|
|
<tbody>
|
|
<tr class="r0 g-first r-even"><th rowspan="4" scope="rowgroup" class="a a-b">0</th><th scope="row" class="c c0">0</th><td class="v0"><span class="opc">$00</span>BRK impl</td><td class="v0 illegal"><span class="opc">$04</span>NOP zpg</td><td class="v0"><span class="opc">$08</span>PHP impl</td><td class="v0 illegal"><span class="opc">$0C</span>NOP abs</td><td class="v0"><span class="opc">$10</span>BPL rel</td><td class="v0 illegal"><span class="opc">$14</span>NOP zpg,X</td><td class="v0"><span class="opc">$18</span>CLC impl</td><td class="v0 illegal"><span class="opc">$1C</span>NOP abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v0"><span class="opc">$01</span>ORA X,ind</td><td class="v0"><span class="opc">$05</span>ORA zpg</td><td class="v0"><span class="opc">$09</span>ORA #</td><td class="v0"><span class="opc">$0D</span>ORA abs</td><td class="v0"><span class="opc">$11</span>ORA ind,Y</td><td class="v0"><span class="opc">$15</span>ORA zpg,X</td><td class="v0"><span class="opc">$19</span>ORA abs,Y</td><td class="v0"><span class="opc">$1D</span>ORA abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v0 illegal"><span class="opc">$02</span>JAM </td><td class="v0"><span class="opc">$06</span>ASL zpg</td><td class="v0"><span class="opc">$0A</span>ASL A</td><td class="v0"><span class="opc">$0E</span>ASL abs</td><td class="v0 illegal"><span class="opc">$12</span>JAM </td><td class="v0"><span class="opc">$16</span>ASL zpg,X</td><td class="v0 illegal"><span class="opc">$1A</span>NOP impl</td><td class="v0"><span class="opc">$1E</span>ASL abs,X</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v0 illegal"><span class="opc">$03</span>SLO X,ind</td><td class="v0 illegal"><span class="opc">$07</span>SLO zpg</td><td class="v0 illegal"><span class="opc">$0B</span>ANC #</td><td class="v0 illegal"><span class="opc">$0F</span>SLO abs</td><td class="v0 illegal"><span class="opc">$13</span>SLO ind,Y</td><td class="v0 illegal"><span class="opc">$17</span>SLO zpg,X</td><td class="v0 illegal"><span class="opc">$1B</span>SLO abs,Y</td><td class="v0 illegal"><span class="opc">$1F</span>SLO abs,X</td></tr>
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<tr class="r0 g-first r-odd"><th rowspan="4" scope="rowgroup" class="a a-b">1</th><th scope="row" class="c c0">0</th><td class="v1"><span class="opc">$20</span>JSR abs</td><td class="v1"><span class="opc">$24</span>BIT zpg</td><td class="v1"><span class="opc">$28</span>PLP impl</td><td class="v1"><span class="opc">$2C</span>BIT abs</td><td class="v1"><span class="opc">$30</span>BMI rel</td><td class="v1 illegal"><span class="opc">$34</span>NOP zpg,X</td><td class="v1"><span class="opc">$38</span>SEC impl</td><td class="v1 illegal"><span class="opc">$3C</span>NOP abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v1"><span class="opc">$21</span>AND X,ind</td><td class="v1"><span class="opc">$25</span>AND zpg</td><td class="v1"><span class="opc">$29</span>AND #</td><td class="v1"><span class="opc">$2D</span>AND abs</td><td class="v1"><span class="opc">$31</span>AND ind,Y</td><td class="v1"><span class="opc">$35</span>AND zpg,X</td><td class="v1"><span class="opc">$39</span>AND abs,Y</td><td class="v1"><span class="opc">$3D</span>AND abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v1 illegal"><span class="opc">$22</span>JAM </td><td class="v1"><span class="opc">$26</span>ROL zpg</td><td class="v1"><span class="opc">$2A</span>ROL A</td><td class="v1"><span class="opc">$2E</span>ROL abs</td><td class="v1 illegal"><span class="opc">$32</span>JAM </td><td class="v1"><span class="opc">$36</span>ROL zpg,X</td><td class="v1 illegal"><span class="opc">$3A</span>NOP impl</td><td class="v1"><span class="opc">$3E</span>ROL abs,X</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v1 illegal"><span class="opc">$23</span>RLA X,ind</td><td class="v1 illegal"><span class="opc">$27</span>RLA zpg</td><td class="v1 illegal"><span class="opc">$2B</span>ANC #</td><td class="v1 illegal"><span class="opc">$2F</span>RLA abs</td><td class="v1 illegal"><span class="opc">$33</span>RLA ind,Y</td><td class="v1 illegal"><span class="opc">$37</span>RLA zpg,X</td><td class="v1 illegal"><span class="opc">$3B</span>RLA abs,Y</td><td class="v1 illegal"><span class="opc">$3F</span>RLA abs,X</td></tr>
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<tr class="r0 g-first r-even"><th rowspan="4" scope="rowgroup" class="a a-b">2</th><th scope="row" class="c c0">0</th><td class="v2"><span class="opc">$40</span>RTI impl</td><td class="v2 illegal"><span class="opc">$44</span>NOP zpg</td><td class="v2"><span class="opc">$48</span>PHA impl</td><td class="v2"><span class="opc">$4C</span>JMP abs</td><td class="v2"><span class="opc">$50</span>BVC rel</td><td class="v2 illegal"><span class="opc">$54</span>NOP zpg,X</td><td class="v2"><span class="opc">$58</span>CLI impl</td><td class="v2 illegal"><span class="opc">$5C</span>NOP abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v2"><span class="opc">$41</span>EOR X,ind</td><td class="v2"><span class="opc">$45</span>EOR zpg</td><td class="v2"><span class="opc">$49</span>EOR #</td><td class="v2"><span class="opc">$4D</span>EOR abs</td><td class="v2"><span class="opc">$51</span>EOR ind,Y</td><td class="v2"><span class="opc">$55</span>EOR zpg,X</td><td class="v2"><span class="opc">$59</span>EOR abs,Y</td><td class="v2"><span class="opc">$5D</span>EOR abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v2 illegal"><span class="opc">$42</span>JAM </td><td class="v2"><span class="opc">$46</span>LSR zpg</td><td class="v2"><span class="opc">$4A</span>LSR A</td><td class="v2"><span class="opc">$4E</span>LSR abs</td><td class="v2 illegal"><span class="opc">$52</span>JAM </td><td class="v2"><span class="opc">$56</span>LSR zpg,X</td><td class="v2 illegal"><span class="opc">$5A</span>NOP impl</td><td class="v2"><span class="opc">$5E</span>LSR abs,X</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v2 illegal"><span class="opc">$43</span>SRE X,ind</td><td class="v2 illegal"><span class="opc">$47</span>SRE zpg</td><td class="v2 illegal"><span class="opc">$4B</span>ALR #</td><td class="v2 illegal"><span class="opc">$4F</span>SRE abs</td><td class="v2 illegal"><span class="opc">$53</span>SRE ind,Y</td><td class="v2 illegal"><span class="opc">$57</span>SRE zpg,X</td><td class="v2 illegal"><span class="opc">$5B</span>SRE abs,Y</td><td class="v2 illegal"><span class="opc">$5F</span>SRE abs,X</td></tr>
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<tr class="r0 g-first r-odd"><th rowspan="4" scope="rowgroup" class="a a-b">3</th><th scope="row" class="c c0">0</th><td class="v3"><span class="opc">$60</span>RTS impl</td><td class="v3 illegal"><span class="opc">$64</span>NOP zpg</td><td class="v3"><span class="opc">$68</span>PLA impl</td><td class="v3"><span class="opc">$6C</span>JMP ind</td><td class="v3"><span class="opc">$70</span>BVS rel</td><td class="v3 illegal"><span class="opc">$74</span>NOP zpg,X</td><td class="v3"><span class="opc">$78</span>SEI impl</td><td class="v3 illegal"><span class="opc">$7C</span>NOP abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v3"><span class="opc">$61</span>ADC X,ind</td><td class="v3"><span class="opc">$65</span>ADC zpg</td><td class="v3"><span class="opc">$69</span>ADC #</td><td class="v3"><span class="opc">$6D</span>ADC abs</td><td class="v3"><span class="opc">$71</span>ADC ind,Y</td><td class="v3"><span class="opc">$75</span>ADC zpg,X</td><td class="v3"><span class="opc">$79</span>ADC abs,Y</td><td class="v3"><span class="opc">$7D</span>ADC abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v3 illegal"><span class="opc">$62</span>JAM </td><td class="v3"><span class="opc">$66</span>ROR zpg</td><td class="v3"><span class="opc">$6A</span>ROR A</td><td class="v3"><span class="opc">$6E</span>ROR abs</td><td class="v3 illegal"><span class="opc">$72</span>JAM </td><td class="v3"><span class="opc">$76</span>ROR zpg,X</td><td class="v3 illegal"><span class="opc">$7A</span>NOP impl</td><td class="v3"><span class="opc">$7E</span>ROR abs,X</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v3 illegal"><span class="opc">$63</span>RRA X,ind</td><td class="v3 illegal"><span class="opc">$67</span>RRA zpg</td><td class="v3 illegal"><span class="opc">$6B</span>ARR #</td><td class="v3 illegal"><span class="opc">$6F</span>RRA abs</td><td class="v3 illegal"><span class="opc">$73</span>RRA ind,Y</td><td class="v3 illegal"><span class="opc">$77</span>RRA zpg,X</td><td class="v3 illegal"><span class="opc">$7B</span>RRA abs,Y</td><td class="v3 illegal"><span class="opc">$7F</span>RRA abs,X</td></tr>
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<tr class="r0 g-first r-even"><th rowspan="4" scope="rowgroup" class="a a-b">4</th><th scope="row" class="c c0">0</th><td class="v4 illegal"><span class="opc">$80</span>NOP #</td><td class="v4"><span class="opc">$84</span>STY zpg</td><td class="v4"><span class="opc">$88</span>DEY impl</td><td class="v4"><span class="opc">$8C</span>STY abs</td><td class="v4"><span class="opc">$90</span>BCC rel</td><td class="v4"><span class="opc">$94</span>STY zpg,X</td><td class="v4"><span class="opc">$98</span>TYA impl</td><td class="v4 illegal"><span class="opc">$9C</span>SHY abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v4"><span class="opc">$81</span>STA X,ind</td><td class="v4"><span class="opc">$85</span>STA zpg</td><td class="v4 illegal"><span class="opc">$89</span>NOP #</td><td class="v4"><span class="opc">$8D</span>STA abs</td><td class="v4"><span class="opc">$91</span>STA ind,Y</td><td class="v4"><span class="opc">$95</span>STA zpg,X</td><td class="v4"><span class="opc">$99</span>STA abs,Y</td><td class="v4"><span class="opc">$9D</span>STA abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v4 illegal"><span class="opc">$82</span>NOP #</td><td class="v4"><span class="opc">$86</span>STX zpg</td><td class="v4"><span class="opc">$8A</span>TXA impl</td><td class="v4"><span class="opc">$8E</span>STX abs</td><td class="v4 illegal"><span class="opc">$92</span>JAM </td><td class="v4"><span class="opc">$96</span>STX zpg,Y</td><td class="v4"><span class="opc">$9A</span>TXS impl</td><td class="v4 illegal"><span class="opc">$9E</span>SHX abs,Y</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v4 illegal"><span class="opc">$83</span>SAX X,ind</td><td class="v4 illegal"><span class="opc">$87</span>SAX zpg</td><td class="v4 illegal"><span class="opc">$8B</span>ANE #</td><td class="v4 illegal"><span class="opc">$8F</span>SAX abs</td><td class="v4 illegal"><span class="opc">$93</span>SHA ind,Y</td><td class="v4 illegal"><span class="opc">$97</span>SAX zpg,Y</td><td class="v4 illegal"><span class="opc">$9B</span>TAS abs,Y</td><td class="v4 illegal"><span class="opc">$9F</span>SHA abs,Y</td></tr>
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<tr class="r0 g-first r-odd"><th rowspan="4" scope="rowgroup" class="a a-b">5</th><th scope="row" class="c c0">0</th><td class="v5"><span class="opc">$A0</span>LDY #</td><td class="v5"><span class="opc">$A4</span>LDY zpg</td><td class="v5"><span class="opc">$A8</span>TAY impl</td><td class="v5"><span class="opc">$AC</span>LDY abs</td><td class="v5"><span class="opc">$B0</span>BCS rel</td><td class="v5"><span class="opc">$B4</span>LDY zpg,X</td><td class="v5"><span class="opc">$B8</span>CLV impl</td><td class="v5"><span class="opc">$BC</span>LDY abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v5"><span class="opc">$A1</span>LDA X,ind</td><td class="v5"><span class="opc">$A5</span>LDA zpg</td><td class="v5"><span class="opc">$A9</span>LDA #</td><td class="v5"><span class="opc">$AD</span>LDA abs</td><td class="v5"><span class="opc">$B1</span>LDA ind,Y</td><td class="v5"><span class="opc">$B5</span>LDA zpg,X</td><td class="v5"><span class="opc">$B9</span>LDA abs,Y</td><td class="v5"><span class="opc">$BD</span>LDA abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v5"><span class="opc">$A2</span>LDX #</td><td class="v5"><span class="opc">$A6</span>LDX zpg</td><td class="v5"><span class="opc">$AA</span>TAX impl</td><td class="v5"><span class="opc">$AE</span>LDX abs</td><td class="v5 illegal"><span class="opc">$B2</span>JAM </td><td class="v5"><span class="opc">$B6</span>LDX zpg,Y</td><td class="v5"><span class="opc">$BA</span>TSX impl</td><td class="v5"><span class="opc">$BE</span>LDX abs,Y</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v5 illegal"><span class="opc">$A3</span>LAX X,ind</td><td class="v5 illegal"><span class="opc">$A7</span>LAX zpg</td><td class="v5 illegal"><span class="opc">$AB</span>LXA #</td><td class="v5 illegal"><span class="opc">$AF</span>LAX abs</td><td class="v5 illegal"><span class="opc">$B3</span>LAX ind,Y</td><td class="v5 illegal"><span class="opc">$B7</span>LAX zpg,Y</td><td class="v5 illegal"><span class="opc">$BB</span>LAS abs,Y</td><td class="v5 illegal"><span class="opc">$BF</span>LAX abs,Y</td></tr>
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<tr class="r0 g-first r-even"><th rowspan="4" scope="rowgroup" class="a a-b">6</th><th scope="row" class="c c0">0</th><td class="v6"><span class="opc">$C0</span>CPY #</td><td class="v6"><span class="opc">$C4</span>CPY zpg</td><td class="v6"><span class="opc">$C8</span>INY impl</td><td class="v6"><span class="opc">$CC</span>CPY abs</td><td class="v6"><span class="opc">$D0</span>BNE rel</td><td class="v6 illegal"><span class="opc">$D4</span>NOP zpg,X</td><td class="v6"><span class="opc">$D8</span>CLD impl</td><td class="v6 illegal"><span class="opc">$DC</span>NOP abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v6"><span class="opc">$C1</span>CMP X,ind</td><td class="v6"><span class="opc">$C5</span>CMP zpg</td><td class="v6"><span class="opc">$C9</span>CMP #</td><td class="v6"><span class="opc">$CD</span>CMP abs</td><td class="v6"><span class="opc">$D1</span>CMP ind,Y</td><td class="v6"><span class="opc">$D5</span>CMP zpg,X</td><td class="v6"><span class="opc">$D9</span>CMP abs,Y</td><td class="v6"><span class="opc">$DD</span>CMP abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v6 illegal"><span class="opc">$C2</span>NOP #</td><td class="v6"><span class="opc">$C6</span>DEC zpg</td><td class="v6"><span class="opc">$CA</span>DEX impl</td><td class="v6"><span class="opc">$CE</span>DEC abs</td><td class="v6 illegal"><span class="opc">$D2</span>JAM </td><td class="v6"><span class="opc">$D6</span>DEC zpg,X</td><td class="v6 illegal"><span class="opc">$DA</span>NOP impl</td><td class="v6"><span class="opc">$DE</span>DEC abs,X</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v6 illegal"><span class="opc">$C3</span>DCP X,ind</td><td class="v6 illegal"><span class="opc">$C7</span>DCP zpg</td><td class="v6 illegal"><span class="opc">$CB</span>SBX #</td><td class="v6 illegal"><span class="opc">$CF</span>DCP abs</td><td class="v6 illegal"><span class="opc">$D3</span>DCP ind,Y</td><td class="v6 illegal"><span class="opc">$D7</span>DCP zpg,X</td><td class="v6 illegal"><span class="opc">$DB</span>DCP abs,Y</td><td class="v6 illegal"><span class="opc">$DF</span>DCP abs,X</td></tr>
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<tr class="r0 g-first r-odd"><th rowspan="4" scope="rowgroup" class="a a-b">7</th><th scope="row" class="c c0">0</th><td class="v7"><span class="opc">$E0</span>CPX #</td><td class="v7"><span class="opc">$E4</span>CPX zpg</td><td class="v7"><span class="opc">$E8</span>INX impl</td><td class="v7"><span class="opc">$EC</span>CPX abs</td><td class="v7"><span class="opc">$F0</span>BEQ rel</td><td class="v7 illegal"><span class="opc">$F4</span>NOP zpg,X</td><td class="v7"><span class="opc">$F8</span>SED impl</td><td class="v7 illegal"><span class="opc">$FC</span>NOP abs,X</td></tr>
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<tr class="r1"><th scope="row" class="c c1">1</th><td class="v7"><span class="opc">$E1</span>SBC X,ind</td><td class="v7"><span class="opc">$E5</span>SBC zpg</td><td class="v7"><span class="opc">$E9</span>SBC #</td><td class="v7"><span class="opc">$ED</span>SBC abs</td><td class="v7"><span class="opc">$F1</span>SBC ind,Y</td><td class="v7"><span class="opc">$F5</span>SBC zpg,X</td><td class="v7"><span class="opc">$F9</span>SBC abs,Y</td><td class="v7"><span class="opc">$FD</span>SBC abs,X</td></tr>
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<tr class="r2"><th scope="row" class="c c2">2</th><td class="v7 illegal"><span class="opc">$E2</span>NOP #</td><td class="v7"><span class="opc">$E6</span>INC zpg</td><td class="v7"><span class="opc">$EA</span>NOP impl</td><td class="v7"><span class="opc">$EE</span>INC abs</td><td class="v7 illegal"><span class="opc">$F2</span>JAM </td><td class="v7"><span class="opc">$F6</span>INC zpg,X</td><td class="v7 illegal"><span class="opc">$FA</span>NOP impl</td><td class="v7"><span class="opc">$FE</span>INC abs,X</td></tr>
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<tr class="r3 g-last"><th scope="row" class="c c3">3</th><td class="v7 illegal"><span class="opc">$E3</span>ISC X,ind</td><td class="v7 illegal"><span class="opc">$E7</span>ISC zpg</td><td class="v7 illegal"><span class="opc">$EB</span>USBC #</td><td class="v7 illegal"><span class="opc">$EF</span>ISC abs</td><td class="v7 illegal"><span class="opc">$F3</span>ISC ind,Y</td><td class="v7 illegal"><span class="opc">$F7</span>ISC zpg,X</td><td class="v7 illegal"><span class="opc">$FB</span>ISC abs,Y</td><td class="v7 illegal"><span class="opc">$FF</span>ISC abs,X</td></tr>
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</tbody>
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</table>
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</div>
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<div class="explanation">
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<p>As a final observation, the two highly unstable instructions "ANE" (XAA) and<br />"LXA" (LAX immediate) involving a "magic constant" are both combinations of<br />an accumulator operation and an inter-register transfer between the<br />accumulator and the X register:</p>
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<p style="margin-left: 1em;">$8B (a=5, c=3, b=2): ANE # = STA # (NOP) + TXA<br />
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(A OR CONST) AND X AND oper <span aria-label="right-hand transfer">-></span> A</p>
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<p style="margin-left: 1em;">$AB (a=4, c=3, b=2): LXA # = LDA # + TAX<br />
|
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(A OR CONST) AND oper <span aria-label="right-hand transfer">-></span> A <span aria-label="right-hand transfer">-></span> X</p>
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<p>In the case of ANE, the contents of the accumulator is put on the internal<br />data lines at the same time as the contents of the X-register, while there's<br />also the operand read for the immediate operation, with the result<br />transferred to the accumulator.</p>
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<p>In the case of LXA, the immediate operand and the contents of the accumulator<br />are competing for the imput lines, while the result will be transferred to<br />both the accumulator and the X register.</p>
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<p>The outcome of these competing, noisy conditions depends on the production<br />series of the chip, and maybe even on environmental conditions. This effects<br />in an OR-ing of the accumulator with the "magic constant" combined with an<br />AND-ing of the competing inputs. The final transfer to the target register(s)<br />then seems to work as may be expected.</p>
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<p>(This AND-ing of competing values susggests that the 6502 is working internally<br />in active negative logic, where all data lines are first set to high and then<br />cleared for any zero bits. This also suggests that the "magic constant" stands<br />merely for a partial transfer of the contents of the accumulator.)</p>
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<p>Much of this also applies to "TAS" (XAS, SHS), $9B, but here the extra cycles<br />for indexed addressing seem to contribute to the conflict being resolved<br />without this "magic constant". However, TAS is still unstable.</p>
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<p>Simlarly the peculiar group involving the high-byte of the provided address + 1<br />(as in "H+1") — SHA (AHX, AXA), SHX (A11, SXA, XAS), SHY (A11, SYA, SAY) —<br />involves a conflict of an attempt to store the accumulator and another register<br />being put on the data lines at the same time, and the operations required to<br />determine the target address for for indexed addressing. Again, the competing<br />values are AND-ed and the instructions are unstable.</p>
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<p>We may also observe that SHY is really the unimplemented instruction "STY abs,X"<br />and SHX is "STX abs,Y" with SHA being the combination of "LDA abs,X" and SHX.</p>
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<p>We may conclude that these "illegal opcodes" or "undocumented instructions" are<br />really a text-book example of undefined behavior for undefined input patterns.<br />Generally speaking, for any instructions xxxxxx11 <em>(c=3)</em> both instructions at<br />xxxxxx01 <em>(c=1)</em> and xxxxxx10 <em>(c=2)</em> are started in a thread, with competing ouput<br />values on the internal data lines AND-ed. For some combinations, this results<br />in a fragile race condition, while others are showing mostly stable behavior.<br />The addressing mode is generally determined by that of the instruction at <em>c=1</em>.</p>
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<p>(It may be interesting that is doesn't matter, if any of the two threads jams,<br />as long as the timing for the other thread resolves. So there is no "JAM"<br /> instruction at <em>c=3</em>.)</p>
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</div>
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<h2 id="pinout">Pinout (NMOS 6502)</h2>
|
|
<figure style="margin: 1em 0 1.5em 1.25em; padding: 0;">
|
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<img src="assets/6502-pinout.png" width="400" height="446" alt="NMOS 6502 Pinout" />
|
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</figure>
|
|
<table class="comparison" aria-label="legend to 6502 pinout">
|
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<tbody>
|
|
<tr><td>Vcc, Vss</td><td>supply voltage (Vcc: +5 V DC ± 5%, Vss: max. +7 V DC)</td></tr>
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<tr><td>Φ<sub>0…2</sub></td><td>clock</td></tr>
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<tr><td>AB0–AB15</td><td>address bus</td></tr>
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<tr><td>DB0–DB7</td><td>data bus</td></tr>
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<tr><td>R/W</td><td>read/write</td></tr>
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<tr><td>RDY</td><td>ready</td></tr>
|
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<tr><td>S.O.</td><td>set overflow (future I/O interface)</td></tr>
|
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<tr><td>SYNC</td><td>sync (goes high on opcode fetch phase)</td></tr>
|
|
<tr><td>I̅R̅Q̅</td><td>interrupt request (active low)</td></tr>
|
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<tr><td>N̅M̅I̅</td><td>non maskable interrupt (active low)</td></tr>
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<tr><td>R̅E̅S̅</td><td>reset (active low)</td></tr>
|
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<tr><td>N.C.</td><td>no connection</td></tr>
|
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</tbody>
|
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</table>
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|
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<p><i>Source: MCS6500 Microcomputer Family Hardware Manual. MOS Technology, Inc., 1976.</i></p>
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<h2 id="family">The 65xx-Family:</h2>
|
|
<table id="mpus" aria-label="annotated table of processor types">
|
|
<thead>
|
|
<tr><th>Type</th><th>Features, Comments</th></tr>
|
|
<thead>
|
|
<tbody>
|
|
<tr><td>6502</td><td>NMOS, 16 bit address bus, 8 bit data bus</td></tr>
|
|
<tr><td>6502A</td><td>accelerated version of 6502</td></tr>
|
|
<tr><td>6502C</td><td>accelerated version of 6502, additional halt pin, CMOS</td></tr>
|
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<tr><td>65C02</td><td>WDC version, additional instructions and address modes, up to 14MHz</td></tr>
|
|
<tr><td>6503, 6505, 6506</td><td>12 bit address bus [4 KiB]</td></tr>
|
|
<tr><td>6504</td><td>13 bit address bus [8 KiB], no NMI</td></tr>
|
|
<tr><td>6507</td><td>13 bit address bus [8 KiB], no interrupt lines</td></tr>
|
|
<tr><td>6509</td><td>20 bit address bus [1 MiB] by bankswitching</td></tr>
|
|
<tr><td>6510</td><td>as 6502 with additional 6 bit I/O-port</td></tr>
|
|
<tr><td>6511</td><td>integrated micro controler with I/O-port, serial interface, and RAM (Rockwell)</td></tr>
|
|
<tr><td>65F11</td><td>as 6511, integrated FORTH interpreter</td></tr>
|
|
<tr><td>7501</td><td>as 6502, HMOS</td></tr>
|
|
<tr><td>8500</td><td>as 6510, CMOS</td></tr>
|
|
<tr><td>8502</td><td>as 6510 with switchable 2 MHz option, 7 bit I/O-port</td></tr>
|
|
<tr><td>65816 (65C816)</td><td>16 bit registers and ALU, 24 bit address bus [16 MiB], up to 24 MHz (Western Design Center)</td></tr>
|
|
<tr><td>65802 (65C802)</td><td>as 65816, pin compatible to 6502, 64 KiB address bus, up to 16 MHz</td></tr>
|
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</tbody>
|
|
</table>
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|
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<h2 id="site-notes">Site Notes</h2>
|
|
<h3>Disclaimer</h3>
|
|
<p>Errors excepted. The information is provided for free and AS IS, therefore without any warranty;<br />without even the implied warranty of merchantability or fitness for a particular purpose.</p>
|
|
|
|
<h3>See also the “Virtual 6502” suite of online-programs</h3>
|
|
<ul class="links" aria-label="related applications">
|
|
<li><a href="./" target="at_masswerk_6502_virtual6502" onclick="if (this.blur) this.blur()">Virtual 6502</a> (6502/6510 emulator)</li>
|
|
<li><a href="assembler.html" target="at_masswerk_6502_assembler" onclick="if (this.blur) this.blur()">6502 Assembler</a></li>
|
|
<li><a href="disassembler.html" target="at_masswerk_6502_dissasembler" onclick="if (this.blur) this.blur()">6502 Disassembler</a></li>
|
|
</ul>
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<h3>External Links</h3>
|
|
<ul class="links" aria-label="related external links">
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<li><a href="http://6502.org/">6502.org</a> — the 6502 microprocessor resource</li>
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<li><a href="http://www.visual6502.org/">visual6502.org</a> — visual transistor-level simulation of the 6502 CPU</lli>
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<li><a href="https://www.westerndesigncenter.com/wdc/">The Western Design Center, Inc.</a> — designers of the 6502 (still thriving)</li>
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</ul>
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<p style="margin-top: 3em;">Presented by <a href="https://www.masswerk.at/" target="_blank">mass:werk</a>.</p>
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