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Add aarch64 division

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Ajai Nelson 2023-03-31 23:25:29 -04:00
parent e6026ec1f9
commit 0302a92cfa
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GPG key ID: 5744FCFB528CB779
1 changed files with 66 additions and 10 deletions
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76
crates/compiler/gen_dev/src/generic64/aarch64.rs
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@ -469,29 +469,29 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
}
fn idiv_reg64_reg64_reg64<'a, 'r, ASM, CC>(
_buf: &mut Vec<'a, u8>,
buf: &mut Vec<'a, u8>,
_storage_manager: &mut StorageManager<'a, 'r, AArch64GeneralReg, AArch64FloatReg, ASM, CC>,
_dst: AArch64GeneralReg,
_src1: AArch64GeneralReg,
_src2: AArch64GeneralReg,
dst: AArch64GeneralReg,
src1: AArch64GeneralReg,
src2: AArch64GeneralReg,
) where
ASM: Assembler<AArch64GeneralReg, AArch64FloatReg>,
CC: CallConv<AArch64GeneralReg, AArch64FloatReg, ASM>,
{
todo!("register signed division for AArch64");
sdiv_reg64_reg64_reg64(buf, dst, src1, src2);
}
fn udiv_reg64_reg64_reg64<'a, 'r, ASM, CC>(
_buf: &mut Vec<'a, u8>,
buf: &mut Vec<'a, u8>,
_storage_manager: &mut StorageManager<'a, 'r, AArch64GeneralReg, AArch64FloatReg, ASM, CC>,
_dst: AArch64GeneralReg,
_src1: AArch64GeneralReg,
_src2: AArch64GeneralReg,
dst: AArch64GeneralReg,
src1: AArch64GeneralReg,
src2: AArch64GeneralReg,
) where
ASM: Assembler<AArch64GeneralReg, AArch64FloatReg>,
CC: CallConv<AArch64GeneralReg, AArch64FloatReg, ASM>,
{
todo!("register unsigned division for AArch64");
udiv_reg64_reg64_reg64(buf, dst, src1, src2);
}
#[inline(always)]
@ -1853,6 +1853,18 @@ fn orr_reg64_reg64_reg64(
buf.extend(inst.bytes());
}
#[inline(always)]
fn sdiv_reg64_reg64_reg64(
buf: &mut Vec<'_, u8>,
dst: AArch64GeneralReg,
src1: AArch64GeneralReg,
src2: AArch64GeneralReg,
) {
let inst = DataProcessingTwoSource::new(0b000011, src2, src1, dst);
buf.extend(inst.bytes());
}
/// `STR Xt, [Xn, #offset]` -> Store Xt to Xn + Offset. ZRSP is SP.
/// Note: imm12 is the offest divided by 8.
#[inline(always)]
@ -1926,6 +1938,18 @@ fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) {
buf.extend(inst.bytes());
}
#[inline(always)]
fn udiv_reg64_reg64_reg64(
buf: &mut Vec<'_, u8>,
dst: AArch64GeneralReg,
src1: AArch64GeneralReg,
src2: AArch64GeneralReg,
) {
let inst = DataProcessingTwoSource::new(0b000010, src2, src1, dst);
buf.extend(inst.bytes());
}
#[cfg(test)]
mod tests {
use super::*;
@ -2412,6 +2436,22 @@ mod tests {
);
}
#[test]
fn test_sdiv_reg64_reg64_reg64() {
disassembler_test!(
sdiv_reg64_reg64_reg64,
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| format!(
"sdiv {}, {}, {}",
reg1.capstone_string(UsesZR),
reg2.capstone_string(UsesZR),
reg3.capstone_string(UsesZR)
),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
}
#[test]
fn test_str_reg64_reg64_imm12() {
disassembler_test!(
@ -2545,4 +2585,20 @@ mod tests {
ALL_GENERAL_REGS
);
}
#[test]
fn test_udiv_reg64_reg64_reg64() {
disassembler_test!(
udiv_reg64_reg64_reg64,
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| format!(
"udiv {}, {}, {}",
reg1.capstone_string(UsesZR),
reg2.capstone_string(UsesZR),
reg3.capstone_string(UsesZR)
),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
}
}