sign extension WIP

crates/compiler/gen_dev/src/generic64/aarch64.rs

@@ -765,6 +765,17 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
         }
     }
 
+    #[inline(always)]
+    fn movsx_reg_reg(
+        _buf: &mut Vec<'_, u8>,
+        _input_width: RegisterWidth,
+        _output_width: RegisterWidth,
+        _dst: AArch64GeneralReg,
+        _src: AArch64GeneralReg,
+    ) {
+        todo!("move with sign extension");
+    }
+
     #[inline(always)]
     fn mov_freg64_base32(_buf: &mut Vec<'_, u8>, _dst: AArch64FloatReg, _offset: i32) {
         todo!("loading floating point reg from base offset for AArch64");

crates/compiler/gen_dev/src/generic64/mod.rs

@@ -288,6 +288,15 @@ pub trait Assembler<GeneralReg: RegTrait, FloatReg: RegTrait>: Sized + Copy {
         Self::mov_reg_reg(buf, RegisterWidth::W8, dst, src);
     }
 
+    // move with sign extension
+    fn movsx_reg_reg(
+        buf: &mut Vec<'_, u8>,
+        input_width: RegisterWidth,
+        output_width: RegisterWidth,
+        dst: GeneralReg,
+        src: GeneralReg,
+    );
+
     // base32 is similar to stack based instructions but they reference the base/frame pointer.
     fn mov_freg64_base32(buf: &mut Vec<'_, u8>, dst: FloatReg, offset: i32);
 
@@ -2993,7 +3002,13 @@ impl<
                     ASM::xor_reg64_reg64_reg64(buf, dst_reg, dst_reg, dst_reg);
 
                     // move the 8-bit integer
-                    ASM::mov_reg_reg(buf, RegisterWidth::W8, dst_reg, src_reg);
+                    ASM::movsx_reg_reg(
+                        buf,
+                        RegisterWidth::W8,
+                        RegisterWidth::W16,
+                        dst_reg,
+                        src_reg,
+                    );
                 }
                 // -- CASTING DOWN --
                 (U64 | I64, I32 | U32) => {

crates/compiler/gen_dev/src/generic64/x86_64.rs

@@ -1490,6 +1490,16 @@ impl Assembler<X86_64GeneralReg, X86_64FloatReg> for X86_64Assembler {
     ) {
         mov_reg_reg(buf, register_width, dst, src);
     }
+    #[inline(always)]
+    fn movsx_reg_reg(
+        buf: &mut Vec<'_, u8>,
+        input_width: RegisterWidth,
+        output_width: RegisterWidth,
+        dst: X86_64GeneralReg,
+        src: X86_64GeneralReg,
+    ) {
+        raw_movsx_reg_reg(buf, input_width, output_width, dst, src);
+    }
 
     #[inline(always)]
     fn mov_freg64_base32(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, offset: i32) {

crates/compiler/test_gen/src/gen_num.rs

@@ -2289,18 +2289,21 @@ num_conversion_tests! {
     "Num.toI16", i16, (
         to_i16_same_width, "15u16", 15, ["gen-wasm", "gen-dev"]
         to_i16_extend, "15i8", 15, ["gen-wasm", "gen-dev"]
+        to_i16_sign_extend, "-15i8", -15, ["gen-wasm", "gen-dev"]
         to_i16_truncate, "115i32", 115, ["gen-wasm", "gen-dev"]
         to_i16_truncate_wraps, "60000i32", -5536, ["gen-wasm", "gen-dev"]
     )
     "Num.toI32", i32, (
         to_i32_same_width, "15u32", 15, ["gen-wasm", "gen-dev"]
         to_i32_extend, "15i8", 15, ["gen-wasm", "gen-dev"]
+        to_i32_sign_extend, "-15i8", -15, ["gen-wasm", "gen-dev"]
         to_i32_truncate, "115i64", 115, ["gen-wasm", "gen-dev"]
         to_i32_truncate_wraps, "5000000000i64", 705032704, ["gen-wasm", "gen-dev"]
     )
     "Num.toI64", i64, (
         to_i64_same_width, "15u64", 15, ["gen-wasm", "gen-dev"]
         to_i64_extend, "15i8", 15, ["gen-wasm", "gen-dev"]
+        to_i64_sign_extend, "-15i8", -15, ["gen-wasm", "gen-dev"]
         to_i64_truncate, "115i128", 115
         to_i64_truncate_wraps, "10_000_000_000_000_000_000i128", -8446744073709551616
     )