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feat: UnconditionalBranchRegister

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rvcas 2021-11-21 15:25:09 -05:00
parent fc81abaf34
commit 1c4a68f15f
1 changed files with 35 additions and 21 deletions
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56
compiler/gen_dev/src/generic64/aarch64.rs
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@ -684,6 +684,37 @@ impl LogicalShiftedRegister {
} }
} }
#[derive(PackedStruct)]
struct UnconditionalBranchRegister {
fixed5: Integer<u8, packed_bits::Bits<5>>,
rn: Integer<u8, packed_bits::Bits<5>>,
m: bool,
a: bool,
fixed4: Integer<u8, packed_bits::Bits<4>>,
fixed3: Integer<u8, packed_bits::Bits<5>>,
op: Integer<u8, packed_bits::Bits<2>>,
fixed2: bool,
z: bool,
fixed: Integer<u8, packed_bits::Bits<7>>,
}
impl UnconditionalBranchRegister {
fn new(op: u8, rn: AArch64GeneralReg) -> Self {
Self {
fixed5: 0b00000.into(),
rn: rn.into(),
m: false,
a: false,
fixed4: 0b0000.into(),
fixed3: 0b11111.into(),
op: op.into(),
fixed2: false,
z: false,
fixed: 0b1101011.into(),
}
}
}
#[derive(PackedStruct, Debug)] #[derive(PackedStruct, Debug)]
struct LoadStoreRegister { struct LoadStoreRegister {
rt: Integer<u8, packed_bits::Bits<5>>, rt: Integer<u8, packed_bits::Bits<5>>,
@ -697,17 +728,6 @@ struct LoadStoreRegister {
size: Integer<u8, packed_bits::Bits<2>>, size: Integer<u8, packed_bits::Bits<2>>,
} }
#[derive(Debug)]
enum BranchGroup {
UnconditionBranchReg {
opc: u8,
op2: u8,
op3: u8,
reg_n: AArch64GeneralReg,
op4: u8,
},
}
#[derive(Debug)] #[derive(Debug)]
enum LdStrGroup { enum LdStrGroup {
UnsignedImm { UnsignedImm {
@ -928,6 +948,7 @@ fn ldr_reg64_imm12(
/// `MOV Xd, Xm` -> Move Xm to Xd. /// `MOV Xd, Xm` -> Move Xm to Xd.
#[inline(always)] #[inline(always)]
fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64GeneralReg) { fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64GeneralReg) {
// MOV is equvalent to `ORR Xd, XZR, XM` in AARCH64.
let inst = LogicalShiftedRegister::new( let inst = LogicalShiftedRegister::new(
LogicalOp::ORR, LogicalOp::ORR,
ShiftType::LSL, ShiftType::LSL,
@ -937,7 +958,6 @@ fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64Ge
dst, dst,
); );
// MOV is equvalent to `ORR Xd, XZR, XM` in AARCH64.
buf.extend(inst.pack().unwrap()); buf.extend(inst.pack().unwrap());
} }
@ -997,15 +1017,9 @@ fn sub_reg64_reg64_imm12(
/// `RET Xn` -> Return to the address stored in Xn. /// `RET Xn` -> Return to the address stored in Xn.
#[inline(always)] #[inline(always)]
fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) { fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) {
buf.extend(&build_instruction(AArch64Instruction::Branch( let inst = UnconditionalBranchRegister::new(0b10, xn);
BranchGroup::UnconditionBranchReg {
opc: 0b0010, buf.extend(inst.pack().unwrap());
op2: 0b11111,
op3: 0b000000,
reg_n: xn,
op4: 0b000,
},
)));
} }
#[cfg(test)] #[cfg(test)]