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5 changed files with 93 additions and 0 deletions
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@ -500,6 +500,16 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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unimplemented!("registers non-equality not implemented yet for AArch64");
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unimplemented!("registers non-equality not implemented yet for AArch64");
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}
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}
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#[inline(always)]
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fn lt_reg64_reg64_reg64(
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_buf: &mut Vec<'_, u8>,
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_dst: AArch64GeneralReg,
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_src1: AArch64GeneralReg,
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_src2: AArch64GeneralReg,
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) {
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unimplemented!("registers less than not implemented yet for AArch64");
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}
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#[inline(always)]
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#[inline(always)]
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fn ret(buf: &mut Vec<'_, u8>) {
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fn ret(buf: &mut Vec<'_, u8>) {
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ret_reg64(buf, AArch64GeneralReg::LR)
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ret_reg64(buf, AArch64GeneralReg::LR)
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@ -179,6 +179,13 @@ pub trait Assembler<GeneralReg: RegTrait, FloatReg: RegTrait> {
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src2: GeneralReg,
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src2: GeneralReg,
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);
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);
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fn lt_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: GeneralReg,
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src1: GeneralReg,
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src2: GeneralReg,
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);
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fn ret(buf: &mut Vec<'_, u8>);
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fn ret(buf: &mut Vec<'_, u8>);
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}
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}
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@ -868,6 +875,25 @@ impl<
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}
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}
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}
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}
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fn build_num_lt(
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&mut self,
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dst: &Symbol,
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src1: &Symbol,
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src2: &Symbol,
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arg_layout: &Layout<'a>,
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) -> Result<(), String> {
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match arg_layout {
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Layout::Builtin(Builtin::Int64) => {
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let dst_reg = self.claim_general_reg(dst)?;
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let src1_reg = self.load_to_general_reg(src1)?;
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let src2_reg = self.load_to_general_reg(src2)?;
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ASM::lt_reg64_reg64_reg64(&mut self.buf, dst_reg, src1_reg, src2_reg);
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Ok(())
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}
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x => Err(format!("NumLt: layout, {:?}, not implemented yet", x)),
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}
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}
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fn create_struct(
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fn create_struct(
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&mut self,
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&mut self,
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sym: &Symbol,
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sym: &Symbol,
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@ -1107,6 +1107,17 @@ impl Assembler<X86_64GeneralReg, X86_64FloatReg> for X86_64Assembler {
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setne_reg64(buf, dst);
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setne_reg64(buf, dst);
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}
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}
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#[inline(always)]
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fn lt_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: X86_64GeneralReg,
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src1: X86_64GeneralReg,
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src2: X86_64GeneralReg,
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) {
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cmp_reg64_reg64(buf, src1, src2);
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setl_reg64(buf, dst);
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}
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#[inline(always)]
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#[inline(always)]
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fn ret(buf: &mut Vec<'_, u8>) {
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fn ret(buf: &mut Vec<'_, u8>) {
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ret(buf);
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ret(buf);
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@ -1498,6 +1509,12 @@ fn setne_reg64(buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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set_reg64_help(buf, reg, 0x95);
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set_reg64_help(buf, reg, 0x95);
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}
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}
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/// `SETL r/m64` -> Set byte if less (SF≠ OF).
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#[inline(always)]
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fn setl_reg64(buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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set_reg64_help(buf, reg, 0x9c);
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}
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/// `RET` -> Near return to calling procedure.
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/// `RET` -> Near return to calling procedure.
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#[inline(always)]
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#[inline(always)]
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fn ret(buf: &mut Vec<'_, u8>) {
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fn ret(buf: &mut Vec<'_, u8>) {
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@ -433,6 +433,23 @@ where
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);
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);
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self.build_neq(sym, &args[0], &args[1], &arg_layouts[0])
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self.build_neq(sym, &args[0], &args[1], &arg_layouts[0])
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}
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}
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LowLevel::NumLt => {
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debug_assert_eq!(
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2,
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args.len(),
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"NumLt: expected to have exactly two argument"
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);
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debug_assert_eq!(
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arg_layouts[0], arg_layouts[1],
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"NumLt: expected all arguments of to have the same layout"
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);
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debug_assert_eq!(
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Layout::Builtin(Builtin::Int1),
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*ret_layout,
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"NumLt: expected to have return layout of type I1"
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);
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self.build_num_lt(sym, &args[0], &args[1], &arg_layouts[0])
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}
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LowLevel::NumRound => self.build_fn_call(
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LowLevel::NumRound => self.build_fn_call(
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sym,
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sym,
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bitcode::NUM_ROUND[FloatWidth::F64].to_string(),
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bitcode::NUM_ROUND[FloatWidth::F64].to_string(),
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@ -523,6 +540,15 @@ where
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arg_layout: &Layout<'a>,
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arg_layout: &Layout<'a>,
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) -> Result<(), String>;
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) -> Result<(), String>;
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/// build_num_lt stores the result of `src1 < src2` into dst.
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fn build_num_lt(
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&mut self,
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dst: &Symbol,
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src1: &Symbol,
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src2: &Symbol,
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arg_layout: &Layout<'a>,
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) -> Result<(), String>;
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/// literal_map gets the map from symbol to literal, used for lazy loading and literal folding.
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/// literal_map gets the map from symbol to literal, used for lazy loading and literal folding.
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fn literal_map(&mut self) -> &mut MutMap<Symbol, Literal<'a>>;
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fn literal_map(&mut self) -> &mut MutMap<Symbol, Literal<'a>>;
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@ -726,6 +726,20 @@ fn gen_int_neq() {
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);
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);
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}
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}
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#[test]
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#[cfg(any(feature = "gen-llvm", feature = "gen-wasm", feature = "gen-dev"))]
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fn gen_int_less_than() {
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assert_evals_to!(
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indoc!(
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r#"
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4 < 5
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"#
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),
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true,
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bool
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);
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}
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#[test]
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#[test]
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#[cfg(any(feature = "gen-llvm"))]
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#[cfg(any(feature = "gen-llvm"))]
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fn gen_dec_eq() {
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fn gen_dec_eq() {
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