dev: box and unbox 32-bit value

crates/compiler/gen_dev/src/generic64/aarch64.rs

@@ -641,6 +641,22 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
         }
     }
     #[inline(always)]
+    fn mov_reg32_mem32_offset32(
+        buf: &mut Vec<'_, u8>,
+        dst: AArch64GeneralReg,
+        src: AArch64GeneralReg,
+        offset: i32,
+    ) {
+        if offset < 0 {
+            todo!("negative mem offsets for AArch64");
+        } else if offset < (0xFFF << 8) {
+            debug_assert!(offset % 8 == 0);
+            ldr_reg64_reg64_imm12(buf, dst, src, (offset as u16) >> 3);
+        } else {
+            todo!("mem offsets over 32k for AArch64");
+        }
+    }
+    #[inline(always)]
     fn mov_mem64_offset32_reg64(
         buf: &mut Vec<'_, u8>,
         dst: AArch64GeneralReg,
@@ -657,6 +673,23 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
         }
     }
 
+    #[inline(always)]
+    fn mov_mem32_offset32_reg32(
+        buf: &mut Vec<'_, u8>,
+        dst: AArch64GeneralReg,
+        offset: i32,
+        src: AArch64GeneralReg,
+    ) {
+        if offset < 0 {
+            todo!("negative mem offsets for AArch64");
+        } else if offset < (0xFFF << 8) {
+            debug_assert!(offset % 8 == 0);
+            str_reg64_reg64_imm12(buf, src, dst, (offset as u16) >> 3);
+        } else {
+            todo!("mem offsets over 32k for AArch64");
+        }
+    }
+
     #[inline(always)]
     fn movsx_reg64_base32(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, offset: i32, size: u8) {
         debug_assert!(size <= 8);

crates/compiler/gen_dev/src/generic64/mod.rs

@@ -240,18 +240,33 @@ pub trait Assembler<GeneralReg: RegTrait, FloatReg: RegTrait>: Sized + Copy {
     fn mov_base32_freg64(buf: &mut Vec<'_, u8>, offset: i32, src: FloatReg);
     fn mov_base32_reg64(buf: &mut Vec<'_, u8>, offset: i32, src: GeneralReg);
 
+    // move from memory (a pointer) to register
     fn mov_reg64_mem64_offset32(
         buf: &mut Vec<'_, u8>,
         dst: GeneralReg,
         src: GeneralReg,
         offset: i32,
     );
+    fn mov_reg32_mem32_offset32(
+        buf: &mut Vec<'_, u8>,
+        dst: GeneralReg,
+        src: GeneralReg,
+        offset: i32,
+    );
+
+    // move from register to memory
     fn mov_mem64_offset32_reg64(
         buf: &mut Vec<'_, u8>,
         dst: GeneralReg,
         offset: i32,
         src: GeneralReg,
     );
+    fn mov_mem32_offset32_reg32(
+        buf: &mut Vec<'_, u8>,
+        dst: GeneralReg,
+        offset: i32,
+        src: GeneralReg,
+    );
 
     /// Sign extends the data at `offset` with `size` as it copies it to `dst`
     /// size must be less than or equal to 8.
@@ -2001,13 +2016,16 @@ impl<
         let element_offset = 0;
 
         // TODO: Expand to all types.
+        let storage_manager = &mut self.storage_manager;
         match self.layout_interner.get(element_layout) {
             Layout::Builtin(Builtin::Int(IntWidth::I64 | IntWidth::U64)) => {
-                let sym_reg = self
-                    .storage_manager
-                    .load_to_general_reg(&mut self.buf, &value);
+                let sym_reg = storage_manager.load_to_general_reg(&mut self.buf, &value);
                 ASM::mov_mem64_offset32_reg64(&mut self.buf, ptr_reg, element_offset, sym_reg);
             }
+            Layout::Builtin(Builtin::Int(IntWidth::I32 | IntWidth::U32)) => {
+                let sym_reg = storage_manager.load_to_general_reg(&mut self.buf, &value);
+                ASM::mov_mem32_offset32_reg32(&mut self.buf, ptr_reg, element_offset, sym_reg);
+            }
             _ if element_width == 0 => {}
             _ if element_width > 8 => {
                 let (from_offset, size) = self.storage_manager.stack_offset_and_size(&value);
@@ -2056,6 +2074,10 @@ impl<
                 let dst_reg = self.storage_manager.claim_general_reg(&mut self.buf, &dst);
                 ASM::mov_reg64_mem64_offset32(&mut self.buf, dst_reg, ptr_reg, 0);
             }
+            Layout::U32 | Layout::I32 => {
+                let dst_reg = self.storage_manager.claim_general_reg(&mut self.buf, &dst);
+                ASM::mov_reg32_mem32_offset32(&mut self.buf, dst_reg, ptr_reg, 0);
+            }
             Layout::STR => {
                 self.storage_manager.with_tmp_general_reg(
                     &mut self.buf,

crates/compiler/gen_dev/src/generic64/x86_64.rs

@@ -1293,6 +1293,16 @@ impl Assembler<X86_64GeneralReg, X86_64FloatReg> for X86_64Assembler {
     ) {
         mov_reg64_base64_offset32(buf, dst, src, offset)
     }
+    #[inline(always)]
+    fn mov_reg32_mem32_offset32(
+        buf: &mut Vec<'_, u8>,
+        dst: X86_64GeneralReg,
+        src: X86_64GeneralReg,
+        offset: i32,
+    ) {
+        mov_reg32_base32_offset32(buf, dst, src, offset)
+    }
+
     #[inline(always)]
     fn mov_mem64_offset32_reg64(
         buf: &mut Vec<'_, u8>,
@@ -1303,6 +1313,16 @@ impl Assembler<X86_64GeneralReg, X86_64FloatReg> for X86_64Assembler {
         mov_base64_offset32_reg64(buf, dst, offset, src)
     }
 
+    #[inline(always)]
+    fn mov_mem32_offset32_reg32(
+        buf: &mut Vec<'_, u8>,
+        dst: X86_64GeneralReg,
+        offset: i32,
+        src: X86_64GeneralReg,
+    ) {
+        mov_base32_offset32_reg32(buf, dst, offset, src)
+    }
+
     #[inline(always)]
     fn movsx_reg64_base32(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, offset: i32, size: u8) {
         debug_assert!(size <= 8);
@@ -2050,6 +2070,27 @@ fn mov_base64_offset32_reg64(
     buf.extend(offset.to_le_bytes());
 }
 
+/// `MOV r/m32,r32` -> Move r32 to r/m32, where m32 references a base + offset.
+#[inline(always)]
+fn mov_base32_offset32_reg32(
+    buf: &mut Vec<'_, u8>,
+    base: X86_64GeneralReg,
+    offset: i32,
+    src: X86_64GeneralReg,
+) {
+    let rex = add_rm_extension(base, REX);
+    let rex = add_reg_extension(src, rex);
+    let src_mod = (src as u8 % 8) << 3;
+    let base_mod = base as u8 % 8;
+    buf.reserve(8);
+    buf.extend([rex, 0x89, 0x80 | src_mod | base_mod]);
+    // Using RSP or R12 requires a secondary index byte.
+    if base == X86_64GeneralReg::RSP || base == X86_64GeneralReg::R12 {
+        buf.push(0x24);
+    }
+    buf.extend(offset.to_le_bytes());
+}
+
 /// `MOV r64,r/m64` -> Move r/m64 to r64, where m64 references a base + offset.
 #[inline(always)]
 fn mov_reg64_base64_offset32(

crates/compiler/test_gen/src/gen_primitives.rs

@@ -3307,10 +3307,16 @@ fn box_str() {
 
 #[test]
 #[cfg(any(feature = "gen-llvm", feature = "gen-wasm", feature = "gen-dev"))]
-fn box_and_unbox_num() {
+fn box_and_unbox_64bit_num() {
     assert_evals_to!("Box.unbox (Box.box (123u64))", 123, u64)
 }
 
+#[test]
+#[cfg(any(feature = "gen-llvm", feature = "gen-wasm", feature = "gen-dev"))]
+fn box_and_unbox_32bit_num() {
+    assert_evals_to!("Box.unbox (Box.box (123u32))", 123, u32)
+}
+
 #[test]
 #[cfg(any(feature = "gen-llvm", feature = "gen-wasm"))]
 fn box_and_unbox_record() {