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fix the order

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Folkert 2023-10-08 20:04:05 +02:00
parent ae4df42eab
commit 6510591b60
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1 changed files with 4 additions and 4 deletions
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8
crates/compiler/gen_dev/src/generic64/aarch64.rs
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@ -438,8 +438,8 @@ impl CallConv<AArch64GeneralReg, AArch64FloatReg, AArch64Assembler> for AArch64C
// All the following stores could be optimized by using `STP` to store pairs.
let w = aligned_stack_size;
AArch64Assembler::mov_stack32_reg64(buf, w - 0x10, AArch64GeneralReg::LR);
AArch64Assembler::mov_stack32_reg64(buf, w - 0x08, AArch64GeneralReg::FP);
AArch64Assembler::mov_stack32_reg64(buf, w - 0x10, AArch64GeneralReg::FP);
AArch64Assembler::mov_stack32_reg64(buf, w - 0x08, AArch64GeneralReg::LR);
// update the frame pointer
AArch64Assembler::add_reg64_reg64_imm32(
@ -478,8 +478,8 @@ impl CallConv<AArch64GeneralReg, AArch64FloatReg, AArch64Assembler> for AArch64C
if aligned_stack_size > 0 {
// All the following stores could be optimized by using `STP` to store pairs.
let w = aligned_stack_size;
AArch64Assembler::mov_reg64_stack32(buf, AArch64GeneralReg::LR, w - 0x10);
AArch64Assembler::mov_reg64_stack32(buf, AArch64GeneralReg::FP, w - 0x08);
AArch64Assembler::mov_reg64_stack32(buf, AArch64GeneralReg::FP, w - 0x10);
AArch64Assembler::mov_reg64_stack32(buf, AArch64GeneralReg::LR, w - 0x08);
let mut offset = aligned_stack_size - fn_call_stack_size;
for reg in saved_general_regs {