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WIP setjmp longjmp roc_panic aarch64 dev
This commit is contained in:
Luke Boswell
Folkert
parent
f1e049ddc9
commit
7de2915fb7
2 changed files with 140 additions and 7 deletions
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@ -647,16 +647,142 @@ impl CallConv<AArch64GeneralReg, AArch64FloatReg, AArch64Assembler> for AArch64C
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}
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}
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fn setjmp(_buf: &mut Vec<'_, u8>) {
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eprintln!("setjmp is not implemented on this target!");
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fn setjmp(buf: &mut Vec<'_, u8>) {
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use AArch64GeneralReg::*;
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type ASM = AArch64Assembler;
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// based on the musl libc setjmp implementation
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//
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// 0000000000211570 <__setjmp>:
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// 211570: a9005013 stp x19, x20, [x0]
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// 211574: a9015815 stp x21, x22, [x0, #16]
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// 211578: a9026017 stp x23, x24, [x0, #32]
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// 21157c: a9036819 stp x25, x26, [x0, #48]
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// 211580: a904701b stp x27, x28, [x0, #64]
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// 211584: a905781d stp x29, x30, [x0, #80]
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// 211588: 910003e2 mov x2, sp
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// 21158c: f9003402 str x2, [x0, #104]
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// 211590: 6d072408 stp d8, d9, [x0, #112]
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// 211594: 6d082c0a stp d10, d11, [x0, #128]
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// 211598: 6d09340c stp d12, d13, [x0, #144]
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// 21159c: 6d0a3c0e stp d14, d15, [x0, #160]
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// 2115a0: d2800000 mov x0, #0x0 // #0
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// 2115a4: d65f03c0 ret
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let env = X0;
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// store caller-saved (i.e. non-volatile) registers
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ASM::mov_mem64_offset32_reg64(buf, env, 0x00, X19);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x08, X20);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x10, X21);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x18, X22);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x20, X23);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x28, X24);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x30, X25);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x38, X26);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x40, X27);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x48, X28);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x50, FP);
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ASM::mov_mem64_offset32_reg64(buf, env, 0x58, LR);
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// mov of sp requires an addition with zero
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ASM::add_reg64_reg64_imm32(buf, X2, ZRSP, 0);
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ASM::mov_mem64_offset32_reg64(buf, env, 104, X2);
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ASM::mov_mem64_offset32_freg64(buf, env, 112, AArch64FloatReg::V8);
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ASM::mov_mem64_offset32_freg64(buf, env, 120, AArch64FloatReg::V9);
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ASM::mov_mem64_offset32_freg64(buf, env, 128, AArch64FloatReg::V10);
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ASM::mov_mem64_offset32_freg64(buf, env, 136, AArch64FloatReg::V11);
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ASM::mov_mem64_offset32_freg64(buf, env, 144, AArch64FloatReg::V12);
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ASM::mov_mem64_offset32_freg64(buf, env, 152, AArch64FloatReg::V13);
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ASM::mov_mem64_offset32_freg64(buf, env, 160, AArch64FloatReg::V14);
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ASM::mov_mem64_offset32_freg64(buf, env, 168, AArch64FloatReg::V15);
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ASM::mov_reg64_imm64(buf, X0, 0);
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ASM::ret(buf)
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}
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fn longjmp(_buf: &mut Vec<'_, u8>) {
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eprintln!("longjmp is not implemented on this target!");
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fn longjmp(buf: &mut Vec<'_, u8>) {
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use AArch64GeneralReg::*;
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type ASM = AArch64Assembler;
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// 0000000000211534 <_longjmp>:
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// 211534: a9405013 ldp x19, x20, [x0]
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// 211538: a9415815 ldp x21, x22, [x0, #16]
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// 21153c: a9426017 ldp x23, x24, [x0, #32]
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// 211540: a9436819 ldp x25, x26, [x0, #48]
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// 211544: a944701b ldp x27, x28, [x0, #64]
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// 211548: a945781d ldp x29, x30, [x0, #80]
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// 21154c: f9403402 ldr x2, [x0, #104]
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// 211550: 9100005f mov sp, x2
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// 211554: 6d472408 ldp d8, d9, [x0, #112]
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// 211558: 6d482c0a ldp d10, d11, [x0, #128]
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// 21155c: 6d49340c ldp d12, d13, [x0, #144]
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// 211560: 6d4a3c0e ldp d14, d15, [x0, #160]
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// 211564: 7100003f cmp w1, #0x0
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// 211568: 1a9f1420 csinc w0, w1, wzr, ne // ne = any
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// 21156c: d61f03c0 br x30
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// load the caller-saved registers
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let env = X0;
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ASM::mov_reg64_mem64_offset32(buf, X19, env, 0x00);
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ASM::mov_reg64_mem64_offset32(buf, X20, env, 0x08);
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ASM::mov_reg64_mem64_offset32(buf, X21, env, 0x10);
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ASM::mov_reg64_mem64_offset32(buf, X22, env, 0x18);
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ASM::mov_reg64_mem64_offset32(buf, X23, env, 0x20);
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ASM::mov_reg64_mem64_offset32(buf, X24, env, 0x28);
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ASM::mov_reg64_mem64_offset32(buf, X25, env, 0x30);
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ASM::mov_reg64_mem64_offset32(buf, X26, env, 0x38);
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ASM::mov_reg64_mem64_offset32(buf, X27, env, 0x40);
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ASM::mov_reg64_mem64_offset32(buf, X28, env, 0x48);
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ASM::mov_reg64_mem64_offset32(buf, FP, env, 0x50);
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ASM::mov_reg64_mem64_offset32(buf, LR, env, 0x58);
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ASM::mov_reg64_mem64_offset32(buf, X2, env, 104);
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ASM::add_reg64_reg64_imm32(buf, ZRSP, X2, 0);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V8, env, 112);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V9, env, 120);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V10, env, 128);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V11, env, 136);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V12, env, 144);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V13, env, 152);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V14, env, 160);
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ASM::mov_freg64_mem64_offset32(buf, AArch64FloatReg::V15, env, 168);
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ASM::mov_reg64_reg64(buf, X0, X10);
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jmp_reg64(buf, ZRSP)
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}
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fn roc_panic(_buf: &mut Vec<'_, u8>, _relocs: &mut Vec<'_, Relocation>) {
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eprintln!("roc_panic is not implemented on this target!");
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fn roc_panic(buf: &mut Vec<'_, u8>, relocs: &mut Vec<'_, Relocation>) {
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use AArch64GeneralReg::*;
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type ASM = AArch64Assembler;
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// move the first argument to roc_panic (a *RocStr) into x9
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ASM::mov_reg64_reg64(buf, X9, X0);
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// move the crash tag into the second return register. We add 1 to it because the 0 value
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// is already used for "no crash occurred"
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ASM::add_reg64_reg64_imm32(buf, X10, X1, 1);
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// the setlongjmp_buffer
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ASM::data_pointer(buf, relocs, String::from("setlongjmp_buffer"), X0);
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ASM::mov_reg64_mem64_offset32(buf, X0, X0, 0);
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// the value to return from the longjmp. It is a pointer to the last 3 words of the setlongjmp_buffer
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// they represent the errore message.
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ASM::mov_reg64_imm64(buf, X2, 170);
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ASM::add_reg64_reg64_reg64(buf, X2, X2, X0);
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for offset in [0, 8, 16] {
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ASM::mov_reg64_mem64_offset32(buf, X11, X9, offset);
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ASM::mov_mem64_offset32_reg64(buf, X2, offset, X11);
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}
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Self::longjmp(buf)
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}
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}
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@ -4099,6 +4225,13 @@ fn scvtf_freg_reg64(
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn jmp_reg64(buf: &mut Vec<'_, u8>, base: AArch64GeneralReg) {
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let inst = 0b11010110000111110000000000000000 | ((base as u32) << 5);
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buf.extend(inst.to_le_bytes());
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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