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fix: add some checks due to potential truncation issues

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rvcas 2021-11-23 14:03:56 -05:00
parent 75778b9c07
commit 8ee01d6ce8
1 changed files with 9 additions and 1 deletions
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10
compiler/gen_dev/src/generic64/aarch64.rs
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@ -545,9 +545,9 @@ impl MoveWideImmediate {
// currently this is done in the assembler above // currently this is done in the assembler above
// assert!(shift % 16 == 0 && shift <= 48); // assert!(shift % 16 == 0 && shift <= 48);
debug_assert!(hw <= 0b11); debug_assert!(hw <= 0b11);
debug_assert!(opc <= 0b11);
Self { Self {
// we want this to truncate, not sure if this does that
reg_d: rd.id().into(), reg_d: rd.id().into(),
imm16, imm16,
hw: hw.into(), hw: hw.into(),
@ -583,6 +583,8 @@ impl ArithmeticImmediate {
imm12: u16, imm12: u16,
sh: bool, sh: bool,
) -> Self { ) -> Self {
debug_assert!(imm12 <= 0xFFF);
Self { Self {
reg_d: rd.id().into(), reg_d: rd.id().into(),
reg_n: rn.id().into(), reg_n: rn.id().into(),
@ -642,6 +644,8 @@ impl ArithmeticShifted {
rn: AArch64GeneralReg, rn: AArch64GeneralReg,
rd: AArch64GeneralReg, rd: AArch64GeneralReg,
) -> Self { ) -> Self {
debug_assert!(imm6 <= 0b111111);
Self { Self {
reg_d: rd.id().into(), reg_d: rd.id().into(),
reg_n: rn.id().into(), reg_n: rn.id().into(),
@ -698,6 +702,8 @@ impl LogicalShiftedRegister {
rn: AArch64GeneralReg, rn: AArch64GeneralReg,
rd: AArch64GeneralReg, rd: AArch64GeneralReg,
) -> Self { ) -> Self {
debug_assert!(imm6 <= 0b111111);
let (op, n) = match op { let (op, n) = match op {
LogicalOp::AND => (0b00, false), LogicalOp::AND => (0b00, false),
LogicalOp::BIC => (0b00, true), LogicalOp::BIC => (0b00, true),
@ -744,6 +750,8 @@ impl Aarch64Bytes for UnconditionalBranchRegister {}
impl UnconditionalBranchRegister { impl UnconditionalBranchRegister {
#[inline(always)] #[inline(always)]
fn new(op: u8, rn: AArch64GeneralReg) -> Self { fn new(op: u8, rn: AArch64GeneralReg) -> Self {
debug_assert!(op <= 0b11);
Self { Self {
fixed5: 0b00000.into(), fixed5: 0b00000.into(),
rn: rn.id().into(), rn: rn.id().into(),