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Revert "implment 8bit logical operators"

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This reverts commit 87c49679e1ac5bcfb710b6d432a9f503db3ee501.
This commit is contained in:
Folkert 2023-02-11 18:32:33 +01:00
parent f6fbfa002b
commit 92539fe3b0
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GPG key ID: 1F17F6FFD112B97C
4 changed files with 1 additions and 138 deletions
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27
crates/compiler/gen_dev/src/generic64/aarch64.rs
View file

@ -963,33 +963,6 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
ret_reg64(buf, AArch64GeneralReg::LR)
}
fn and_reg8_reg8_reg8(
_buf: &mut Vec<'_, u8>,
_dst: AArch64GeneralReg,
_src1: AArch64GeneralReg,
_src2: AArch64GeneralReg,
) {
todo!("bitwise and for AArch64")
}
fn or_reg8_reg8_reg8(
_buf: &mut Vec<'_, u8>,
_dst: AArch64GeneralReg,
_src1: AArch64GeneralReg,
_src2: AArch64GeneralReg,
) {
todo!("bitwise and for AArch64")
}
fn xor_reg8_reg8_reg8(
_buf: &mut Vec<'_, u8>,
_dst: AArch64GeneralReg,
_src1: AArch64GeneralReg,
_src2: AArch64GeneralReg,
) {
todo!("bitwise and for AArch64")
}
fn and_reg64_reg64_reg64(
_buf: &mut Vec<'_, u8>,
_dst: AArch64GeneralReg,

21
crates/compiler/gen_dev/src/generic64/mod.rs
View file

@ -148,27 +148,6 @@ pub trait Assembler<GeneralReg: RegTrait, FloatReg: RegTrait>: Sized + Copy {
src2: GeneralReg,
);
fn and_reg8_reg8_reg8(
buf: &mut Vec<'_, u8>,
dst: GeneralReg,
src1: GeneralReg,
src2: GeneralReg,
);
fn or_reg8_reg8_reg8(
buf: &mut Vec<'_, u8>,
dst: GeneralReg,
src1: GeneralReg,
src2: GeneralReg,
);
fn xor_reg8_reg8_reg8(
buf: &mut Vec<'_, u8>,
dst: GeneralReg,
src1: GeneralReg,
src2: GeneralReg,
);
fn and_reg64_reg64_reg64(
buf: &mut Vec<'_, u8>,
dst: GeneralReg,

89
crates/compiler/gen_dev/src/generic64/x86_64.rs
View file

@ -1567,18 +1567,6 @@ impl Assembler<X86_64GeneralReg, X86_64FloatReg> for X86_64Assembler {
seto_reg64(buf, dst);
}
fn and_reg8_reg8_reg8(buf: &mut Vec<'_, u8>, dst: Reg64, src1: Reg64, src2: Reg64) {
binop_move_src_to_dst_reg64(buf, and_reg8_reg8, dst, src1, src2)
}
fn or_reg8_reg8_reg8(buf: &mut Vec<'_, u8>, dst: Reg64, src1: Reg64, src2: Reg64) {
binop_move_src_to_dst_reg64(buf, or_reg8_reg8, dst, src1, src2)
}
fn xor_reg8_reg8_reg8(buf: &mut Vec<'_, u8>, dst: Reg64, src1: Reg64, src2: Reg64) {
binop_move_src_to_dst_reg64(buf, xor_reg8_reg8, dst, src1, src2)
}
fn and_reg64_reg64_reg64(buf: &mut Vec<'_, u8>, dst: Reg64, src1: Reg64, src2: Reg64) {
binop_move_src_to_dst_reg64(buf, and_reg64_reg64, dst, src1, src2)
}
@ -1723,20 +1711,6 @@ fn add_reg_extension<T: RegTrait>(reg: T, byte: u8) -> u8 {
}
}
#[inline(always)]
fn binop_reg8_reg8(
op_code: u8,
buf: &mut Vec<'_, u8>,
dst: X86_64GeneralReg,
src: X86_64GeneralReg,
) {
let rex = add_rm_extension(dst, REX);
let rex = add_reg_extension(src, rex);
let dst_mod = dst as u8 % 8;
let src_mod = (src as u8 % 8) << 3;
buf.extend([rex, op_code, 0xC0 | dst_mod | src_mod]);
}
#[inline(always)]
fn binop_reg64_reg64(
op_code: u8,
@ -1788,27 +1762,6 @@ fn add_reg64_reg64(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, src: X86_64Gene
binop_reg64_reg64(0x01, buf, dst, src);
}
/// `AND r/m8,r8` -> Bitwise logical and r8 to r/m8.
#[inline(always)]
fn and_reg8_reg8(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, src: X86_64GeneralReg) {
// NOTE: src and dst are flipped by design
binop_reg8_reg8(0x22, buf, src, dst);
}
/// `OR r/m8,r8` -> Bitwise logical inclusive or r8 to r/m8.
#[inline(always)]
fn or_reg8_reg8(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, src: X86_64GeneralReg) {
// NOTE: src and dst are flipped by design
binop_reg8_reg8(0x0A, buf, src, dst);
}
/// `XOR r/m8,r8` -> Bitwise logical exclusive or r8 to r/m8.
#[inline(always)]
fn xor_reg8_reg8(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, src: X86_64GeneralReg) {
// NOTE: src and dst are flipped by design
binop_reg8_reg8(0x32, buf, src, dst);
}
/// `AND r/m64,r64` -> Bitwise logical and r64 to r/m64.
#[inline(always)]
fn and_reg64_reg64(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, src: X86_64GeneralReg) {
@ -2889,48 +2842,6 @@ mod tests {
);
}
#[test]
fn test_and_reg8_reg8() {
disassembler_test!(
and_reg8_reg8,
|reg1, reg2| format!(
"and {}, {}",
X86_64GeneralReg::low_8bits_string(&reg1),
X86_64GeneralReg::low_8bits_string(&reg2),
),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
}
#[test]
fn test_or_reg8_reg8() {
disassembler_test!(
or_reg8_reg8,
|reg1, reg2| format!(
"or {}, {}",
X86_64GeneralReg::low_8bits_string(&reg1),
X86_64GeneralReg::low_8bits_string(&reg2),
),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
}
#[test]
fn test_xor_reg8_reg8() {
disassembler_test!(
xor_reg8_reg8,
|reg1, reg2| format!(
"xor {}, {}",
X86_64GeneralReg::low_8bits_string(&reg1),
X86_64GeneralReg::low_8bits_string(&reg2),
),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
}
#[test]
fn test_or_reg64_reg64() {
disassembler_test!(

2
crates/compiler/test_gen/src/gen_str.rs
View file

@ -1857,7 +1857,7 @@ fn str_walk_utf8_with_index() {
}
#[test]
#[cfg(any(feature = "gen-llvm", feature = "gen-dev"))]
#[cfg(any(feature = "gen-llvm"))]
fn str_append_scalar() {
assert_evals_to!(
indoc!(