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Start adding more gen_dev aarch64 instructions
This commit is contained in:
Ajai Nelson
parent
47dd461a4a
commit
9a6edbd220
2 changed files with 609 additions and 0 deletions
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@ -1221,6 +1221,203 @@ impl ArithmeticShifted {
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}
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}
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// ARM manual section C1.2.4
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#[derive(Copy, Clone, PartialEq)]
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enum ConditionCode {
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EQ = 0b0000,
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NE = 0b0001,
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CSHS = 0b0010,
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CCLO = 0b0011,
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MI = 0b0100,
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PL = 0b0101,
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VS = 0b0110,
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VC = 0b0111,
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HI = 0b1000,
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LS = 0b1001,
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GE = 0b1010,
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LT = 0b1011,
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GT = 0b1100,
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LE = 0b1101,
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AL = 0b1110,
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}
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impl ConditionCode {
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#[inline(always)]
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fn id(&self) -> u8 {
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*self as u8
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}
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fn invert(self) -> Self {
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// TODO: check
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match self {
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ConditionCode::EQ => ConditionCode::NE,
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ConditionCode::NE => ConditionCode::EQ,
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ConditionCode::CSHS => ConditionCode::CCLO,
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ConditionCode::CCLO => ConditionCode::CSHS,
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ConditionCode::MI => ConditionCode::PL,
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ConditionCode::PL => ConditionCode::MI,
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ConditionCode::VS => ConditionCode::VC,
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ConditionCode::VC => ConditionCode::VS,
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ConditionCode::HI => ConditionCode::LS,
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ConditionCode::LS => ConditionCode::HI,
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ConditionCode::GE => ConditionCode::LT,
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ConditionCode::LT => ConditionCode::GE,
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ConditionCode::GT => ConditionCode::LE,
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ConditionCode::LE => ConditionCode::GT,
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ConditionCode::AL => ConditionCode::AL,
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}
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}
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}
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impl std::fmt::Display for ConditionCode {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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write!(
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f,
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"{}",
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match self {
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ConditionCode::EQ => "eq",
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ConditionCode::NE => "ne",
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ConditionCode::CSHS => "hs",
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ConditionCode::CCLO => "lo",
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ConditionCode::MI => "mi",
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ConditionCode::PL => "pl",
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ConditionCode::VS => "vs",
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ConditionCode::VC => "vc",
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ConditionCode::HI => "hi",
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ConditionCode::LS => "ls",
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ConditionCode::GE => "ge",
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ConditionCode::LT => "lt",
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ConditionCode::GT => "gt",
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ConditionCode::LE => "le",
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ConditionCode::AL => "al",
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}
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)
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}
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}
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const ALL_CONDITIONS: &'static [ConditionCode] = &[
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ConditionCode::EQ,
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ConditionCode::NE,
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ConditionCode::CSHS,
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ConditionCode::CCLO,
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ConditionCode::MI,
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ConditionCode::PL,
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ConditionCode::VS,
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ConditionCode::VC,
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ConditionCode::HI,
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ConditionCode::LS,
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ConditionCode::GE,
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ConditionCode::LT,
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ConditionCode::GT,
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ConditionCode::LE,
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ConditionCode::AL,
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];
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#[derive(PackedStruct)]
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#[packed_struct(endian = "msb")]
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pub struct ConditionalBranchImmediate {
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fixed: Integer<u8, packed_bits::Bits<7>>,
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o1: bool,
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imm19: Integer<u32, packed_bits::Bits<19>>,
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o0: bool,
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cond: Integer<u8, packed_bits::Bits<4>>,
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}
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impl Aarch64Bytes for ConditionalBranchImmediate {}
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impl ConditionalBranchImmediate {
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#[inline(always)]
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fn new(cond: ConditionCode, imm19: u32) -> Self {
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debug_assert!(imm19 >> 19 == 0);
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Self {
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cond: cond.id().into(),
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o0: false,
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imm19: imm19.into(),
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o1: false,
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fixed: 0b0101010.into(),
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}
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}
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}
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#[derive(PackedStruct)]
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#[packed_struct(endian = "msb")]
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pub struct ConditionalSelect {
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sf: bool,
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op: bool,
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s: bool,
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fixed: Integer<u8, packed_bits::Bits<8>>,
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reg_m: Integer<u8, packed_bits::Bits<5>>,
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cond: Integer<u8, packed_bits::Bits<4>>,
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op2: Integer<u8, packed_bits::Bits<2>>,
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reg_n: Integer<u8, packed_bits::Bits<5>>,
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reg_d: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for ConditionalSelect {}
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impl ConditionalSelect {
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#[inline(always)]
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fn new(
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op: bool,
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s: bool,
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cond: ConditionCode,
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op2: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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) -> Self {
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debug_assert!(op2 <= 0b11);
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Self {
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reg_d: rd.id().into(),
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reg_n: rn.id().into(),
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op2: op2.into(),
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cond: cond.id().into(),
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reg_m: rm.id().into(),
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fixed: 0b11010100.into(),
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s,
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op,
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// true for 64 bit addition
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// false for 32 bit addition
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sf: true,
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}
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}
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}
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#[derive(PackedStruct)]
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#[packed_struct(endian = "msb")]
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pub struct DataProcessingTwoSource {
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sf: bool,
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fixed: bool,
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s: bool,
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fixed2: Integer<u8, packed_bits::Bits<8>>,
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reg_m: Integer<u8, packed_bits::Bits<5>>,
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op: Integer<u8, packed_bits::Bits<6>>,
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reg_n: Integer<u8, packed_bits::Bits<5>>,
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reg_d: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for DataProcessingTwoSource {}
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impl DataProcessingTwoSource {
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#[inline(always)]
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fn new(op: u8, rm: AArch64GeneralReg, rn: AArch64GeneralReg, rd: AArch64GeneralReg) -> Self {
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debug_assert!(op <= 0b111111);
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Self {
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sf: true,
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fixed: false,
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s: false,
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fixed2: 0b11010110.into(),
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reg_m: rm.id().into(),
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op: op.into(),
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reg_n: rn.id().into(),
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reg_d: rd.id().into(),
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}
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}
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}
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#[derive(Debug)]
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#[allow(dead_code)]
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enum LogicalOp {
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@ -1325,6 +1522,28 @@ impl UnconditionalBranchRegister {
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}
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}
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#[derive(PackedStruct)]
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#[packed_struct(endian = "msb")]
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pub struct UnconditionalBranchImmediate {
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op: bool, // false=B, true=BL
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fixed: Integer<u8, packed_bits::Bits<5>>,
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imm26: Integer<u32, packed_bits::Bits<26>>,
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}
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impl Aarch64Bytes for UnconditionalBranchImmediate {}
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impl UnconditionalBranchImmediate {
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#[inline(always)]
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fn new(op: bool, imm26: u32) -> Self {
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debug_assert!(imm26 <= 0b11_1111_1111_1111_1111_1111_1111);
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Self {
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op,
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fixed: 0b00101.into(),
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imm26: imm26.into(),
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}
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}
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}
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// Uses unsigned Offset
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// opc = 0b01 means load
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// opc = 0b00 means store
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@ -1404,6 +1623,92 @@ fn add_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn and_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = LogicalShiftedRegister::new(LogicalOp::AND, ShiftType::LSL, 0, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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/// TODO
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#[inline(always)]
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fn b_cond(buf: &mut Vec<'_, u8>, cond: ConditionCode, imm19: i32) {
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debug_assert!(imm19 & 0b11 == 0, "branch location must be 4-byte aligned");
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let shifted = imm19 >> 2;
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let unsigned = shifted as u32;
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let left_removed = (unsigned << 13) >> 13;
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if imm19 >= 0 {
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debug_assert!(left_removed == unsigned);
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} else {
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debug_assert!(left_removed | 0b1111_1111_1111_1100_0000_0000_0000_0000 == unsigned);
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}
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let inst = ConditionalBranchImmediate::new(cond, left_removed);
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buf.extend(inst.bytes());
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}
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/// `B imm26` -> Jump to PC + imm26.
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#[inline(always)]
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fn b_imm26(buf: &mut Vec<'_, u8>, imm26: i32) {
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debug_assert!(imm26 & 0b11 == 0, "branch location must be 4-byte aligned");
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let shifted = imm26 >> 2;
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let unsigned = shifted as u32;
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let left_removed = (unsigned << 6) >> 6;
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if imm26 >= 0 {
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debug_assert!(left_removed == unsigned);
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} else {
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debug_assert!(left_removed | 0b1111_1110_0000_0000_0000_0000_0000_0000 == unsigned);
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}
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let inst = UnconditionalBranchImmediate::new(false, left_removed);
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn csinc_reg64_reg64_reg64_cond(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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cond: ConditionCode,
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) {
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let inst = ConditionalSelect::new(false, false, cond, 0b01, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn csneg_reg64_reg64_reg64_cond(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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cond: ConditionCode,
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) {
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let inst = ConditionalSelect::new(true, false, cond, 0b01, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn eor_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = LogicalShiftedRegister::new(LogicalOp::EOR, ShiftType::LSL, 0, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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/// `LDR Xt, [Xn, #offset]` -> Load Xn + Offset Xt. ZRSP is SP.
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/// Note: imm12 is the offest divided by 8.
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#[inline(always)]
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@ -1418,6 +1723,42 @@ fn ldr_reg64_reg64_imm12(
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn lsl_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001000, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn lsr_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001001, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn asr_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001010, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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/// `MOV Xd, Xm` -> Move Xm to Xd.
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#[inline(always)]
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fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64GeneralReg) {
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@ -1450,6 +1791,18 @@ fn movz_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, h
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn orr_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = LogicalShiftedRegister::new(LogicalOp::ORR, ShiftType::LSL, 0, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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/// `STR Xt, [Xn, #offset]` -> Store Xt to Xn + Offset. ZRSP is SP.
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/// Note: imm12 is the offest divided by 8.
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#[inline(always)]
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@ -1490,6 +1843,19 @@ fn sub_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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/// `SUBS Xd, Xn, imm12` ->
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#[inline(always)]
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fn subs_reg64_reg64_imm12(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src: AArch64GeneralReg,
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imm12: u16,
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) {
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let inst = ArithmeticImmediate::new(true, true, dst, src, imm12, false);
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buf.extend(inst.bytes());
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}
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/// `RET Xn` -> Return to the address stored in Xn.
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#[inline(always)]
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fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) {
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@ -1612,6 +1978,146 @@ mod tests {
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);
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}
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#[test]
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fn test_and_reg64_reg64_reg64() {
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disassembler_test!(
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and_reg64_reg64_reg64,
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|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| format!(
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"and {}, {}, {}",
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reg1.capstone_string(UsesZR),
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reg2.capstone_string(UsesZR),
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reg3.capstone_string(UsesZR)
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),
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ALL_GENERAL_REGS,
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ALL_GENERAL_REGS,
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ALL_GENERAL_REGS
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);
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}
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#[test]
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fn test_asr_reg64_reg64_reg64() {
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disassembler_test!(
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asr_reg64_reg64_reg64,
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|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| format!(
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"asr {}, {}, {}",
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reg1.capstone_string(UsesZR),
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reg2.capstone_string(UsesZR),
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reg3.capstone_string(UsesZR)
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),
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ALL_GENERAL_REGS,
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ALL_GENERAL_REGS,
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ALL_GENERAL_REGS
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);
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}
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#[test]
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fn test_b_cond() {
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disassembler_test!(
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b_cond,
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|cond: ConditionCode, imm: i32| format!("b.{} #0x{:x}", cond, imm as i64),
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ALL_CONDITIONS,
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[0x120, -0x120, (1 << 20) - 4, -(1 << 20)]
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);
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}
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#[test]
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fn test_b_imm26() {
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disassembler_test!(
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b_imm26,
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|imm| format!("b #0x{:x}", imm as i64),
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[0x120, -0x120, (1 << 27) - 4, -(1 << 27)]
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);
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}
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#[test]
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fn test_csinc() {
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disassembler_test!(
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csinc_reg64_reg64_reg64_cond,
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|reg1: AArch64GeneralReg,
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reg2: AArch64GeneralReg,
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reg3: AArch64GeneralReg,
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cond: ConditionCode| {
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if reg3 != AArch64GeneralReg::ZRSP
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&& cond != ConditionCode::AL
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&& reg2 != AArch64GeneralReg::ZRSP
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&& reg2 == reg3
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{
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format!(
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"cinc {}, {}, {}",
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reg1.capstone_string(UsesZR),
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reg2.capstone_string(UsesZR),
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cond.invert()
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)
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} else if reg3 == AArch64GeneralReg::ZRSP
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&& cond != ConditionCode::AL
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||||
&& reg2 == AArch64GeneralReg::ZRSP
|
||||
{
|
||||
format!("cset {}, {}", reg1.capstone_string(UsesZR), cond.invert())
|
||||
} else {
|
||||
format!(
|
||||
"csinc {}, {}, {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesZR),
|
||||
reg3.capstone_string(UsesZR),
|
||||
cond
|
||||
)
|
||||
}
|
||||
},
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_CONDITIONS
|
||||
)
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_csneg() {
|
||||
disassembler_test!(
|
||||
csneg_reg64_reg64_reg64_cond,
|
||||
|reg1: AArch64GeneralReg,
|
||||
reg2: AArch64GeneralReg,
|
||||
reg3: AArch64GeneralReg,
|
||||
cond: ConditionCode| {
|
||||
if cond != ConditionCode::AL && reg2 == reg3 {
|
||||
format!(
|
||||
"cneg {}, {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesZR),
|
||||
cond.invert()
|
||||
)
|
||||
} else {
|
||||
format!(
|
||||
"csneg {}, {}, {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesZR),
|
||||
reg3.capstone_string(UsesZR),
|
||||
cond
|
||||
)
|
||||
}
|
||||
},
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_CONDITIONS
|
||||
)
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_eor_reg64_reg64_reg64() {
|
||||
disassembler_test!(
|
||||
eor_reg64_reg64_reg64,
|
||||
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| format!(
|
||||
"eor {}, {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesZR),
|
||||
reg3.capstone_string(UsesZR)
|
||||
),
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_ldr_reg64_reg64_imm12() {
|
||||
disassembler_test!(
|
||||
|
|
@ -1628,6 +2134,38 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_lsl_reg64_reg64_reg64() {
|
||||
disassembler_test!(
|
||||
lsl_reg64_reg64_reg64,
|
||||
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| format!(
|
||||
"lsl {}, {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesZR),
|
||||
reg3.capstone_string(UsesZR)
|
||||
),
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_lsr_reg64_reg64_reg64() {
|
||||
disassembler_test!(
|
||||
lsr_reg64_reg64_reg64,
|
||||
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| format!(
|
||||
"lsr {}, {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesZR),
|
||||
reg3.capstone_string(UsesZR)
|
||||
),
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_mov_reg64_reg64() {
|
||||
disassembler_test!(
|
||||
|
|
@ -1678,6 +2216,32 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_orr_reg64_reg64_reg64() {
|
||||
disassembler_test!(
|
||||
orr_reg64_reg64_reg64,
|
||||
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| {
|
||||
if reg2 == AArch64GeneralReg::ZRSP {
|
||||
format!(
|
||||
"mov {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg3.capstone_string(UsesZR),
|
||||
)
|
||||
} else {
|
||||
format!(
|
||||
"orr {}, {}, {}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesZR),
|
||||
reg3.capstone_string(UsesZR),
|
||||
)
|
||||
}
|
||||
},
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_str_reg64_reg64_imm12() {
|
||||
disassembler_test!(
|
||||
|
|
@ -1738,6 +2302,31 @@ mod tests {
|
|||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
|
||||
fn test_subs_reg64_reg64_imm12() {
|
||||
disassembler_test!(
|
||||
subs_reg64_reg64_imm12,
|
||||
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, imm| {
|
||||
if reg1 == AArch64GeneralReg::ZRSP {
|
||||
// When the first register is SP, it gets disassembled as cmp,
|
||||
// which is an alias for subs.
|
||||
format!("cmp {}, #0x{:x}", reg2.capstone_string(UsesSP), imm)
|
||||
} else {
|
||||
format!(
|
||||
"subs {}, {}, #0x{:x}",
|
||||
reg1.capstone_string(UsesZR),
|
||||
reg2.capstone_string(UsesSP),
|
||||
imm
|
||||
)
|
||||
}
|
||||
},
|
||||
ALL_GENERAL_REGS,
|
||||
ALL_GENERAL_REGS,
|
||||
[0x123]
|
||||
);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_ret_reg64() {
|
||||
disassembler_test!(
|
||||
|
|
|
|||
|
|
@ -77,4 +77,24 @@ macro_rules! disassembler_test {
|
|||
}
|
||||
}
|
||||
}};
|
||||
($assemble_fn: expr, $format_fn: expr, $iter:expr, $iter2:expr, $iter3:expr, $iter4:expr) => {{
|
||||
use $crate::generic64::disassembler_test_macro::merge_instructions_without_line_numbers;
|
||||
let arena = bumpalo::Bump::new();
|
||||
let (mut buf, cs) = setup_capstone_and_arena(&arena);
|
||||
for i in $iter.iter() {
|
||||
for i2 in $iter2.iter() {
|
||||
for i3 in $iter3.iter() {
|
||||
for i4 in $iter4.iter() {
|
||||
buf.clear();
|
||||
$assemble_fn(&mut buf, *i, *i2, *i3, *i4);
|
||||
let instructions = cs.disasm_all(&buf, 0).unwrap();
|
||||
assert_eq!(
|
||||
$format_fn(*i, *i2, *i3, *i4),
|
||||
merge_instructions_without_line_numbers(instructions)
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}};
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue