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move with sign extension
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Folkert
parent
f30b0bdf68
commit
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1 changed files with 249 additions and 51 deletions
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@ -52,51 +52,92 @@ pub enum AArch64GeneralReg {
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ZRSP = 31,
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}
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impl AArch64GeneralReg {
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#[cfg(test)]
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const fn as_str_32bit(&self) -> &str {
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match self {
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AArch64GeneralReg::X0 => "w0",
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AArch64GeneralReg::X1 => "w1",
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AArch64GeneralReg::X2 => "w2",
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AArch64GeneralReg::X3 => "w3",
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AArch64GeneralReg::X4 => "w4",
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AArch64GeneralReg::X5 => "w5",
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AArch64GeneralReg::X6 => "w6",
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AArch64GeneralReg::X7 => "w7",
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AArch64GeneralReg::XR => "wr",
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AArch64GeneralReg::X9 => "w9",
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AArch64GeneralReg::X10 => "w10",
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AArch64GeneralReg::X11 => "w11",
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AArch64GeneralReg::X12 => "w12",
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AArch64GeneralReg::X13 => "w13",
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AArch64GeneralReg::X14 => "w14",
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AArch64GeneralReg::X15 => "w15",
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AArch64GeneralReg::IP0 => "ip0",
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AArch64GeneralReg::IP1 => "ip1",
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AArch64GeneralReg::PR => "pr",
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AArch64GeneralReg::X19 => "w19",
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AArch64GeneralReg::X20 => "w20",
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AArch64GeneralReg::X21 => "w21",
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AArch64GeneralReg::X22 => "w22",
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AArch64GeneralReg::X23 => "w23",
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AArch64GeneralReg::X24 => "w24",
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AArch64GeneralReg::X25 => "w25",
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AArch64GeneralReg::X26 => "w26",
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AArch64GeneralReg::X27 => "w27",
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AArch64GeneralReg::X28 => "w28",
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AArch64GeneralReg::FP => "fp",
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AArch64GeneralReg::LR => "lr",
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AArch64GeneralReg::ZRSP => "zrsp",
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}
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}
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const fn as_str_64bit(&self) -> &str {
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match self {
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AArch64GeneralReg::X0 => "x0",
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AArch64GeneralReg::X1 => "x1",
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AArch64GeneralReg::X2 => "x2",
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AArch64GeneralReg::X3 => "x3",
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AArch64GeneralReg::X4 => "x4",
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AArch64GeneralReg::X5 => "x5",
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AArch64GeneralReg::X6 => "x6",
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AArch64GeneralReg::X7 => "x7",
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AArch64GeneralReg::XR => "xr",
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AArch64GeneralReg::X9 => "x9",
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AArch64GeneralReg::X10 => "x10",
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AArch64GeneralReg::X11 => "x11",
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AArch64GeneralReg::X12 => "x12",
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AArch64GeneralReg::X13 => "x13",
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AArch64GeneralReg::X14 => "x14",
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AArch64GeneralReg::X15 => "x15",
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AArch64GeneralReg::IP0 => "ip0",
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AArch64GeneralReg::IP1 => "ip1",
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AArch64GeneralReg::PR => "pr",
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AArch64GeneralReg::X19 => "x19",
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AArch64GeneralReg::X20 => "x20",
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AArch64GeneralReg::X21 => "x21",
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AArch64GeneralReg::X22 => "x22",
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AArch64GeneralReg::X23 => "x23",
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AArch64GeneralReg::X24 => "x24",
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AArch64GeneralReg::X25 => "x25",
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AArch64GeneralReg::X26 => "x26",
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AArch64GeneralReg::X27 => "x27",
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AArch64GeneralReg::X28 => "x28",
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AArch64GeneralReg::FP => "fp",
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AArch64GeneralReg::LR => "lr",
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AArch64GeneralReg::ZRSP => "zrsp",
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}
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}
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}
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impl RegTrait for AArch64GeneralReg {
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fn value(&self) -> u8 {
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*self as u8
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}
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}
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impl std::fmt::Display for AArch64GeneralReg {
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fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {
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write!(
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f,
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"{}",
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match self {
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AArch64GeneralReg::X0 => "x0",
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AArch64GeneralReg::X1 => "x1",
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AArch64GeneralReg::X2 => "x2",
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AArch64GeneralReg::X3 => "x3",
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AArch64GeneralReg::X4 => "x4",
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AArch64GeneralReg::X5 => "x5",
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AArch64GeneralReg::X6 => "x6",
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AArch64GeneralReg::X7 => "x7",
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AArch64GeneralReg::XR => "xr",
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AArch64GeneralReg::X9 => "x9",
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AArch64GeneralReg::X10 => "x10",
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AArch64GeneralReg::X11 => "x11",
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AArch64GeneralReg::X12 => "x12",
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AArch64GeneralReg::X13 => "x13",
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AArch64GeneralReg::X14 => "x14",
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AArch64GeneralReg::X15 => "x15",
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AArch64GeneralReg::IP0 => "ip0",
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AArch64GeneralReg::IP1 => "ip1",
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AArch64GeneralReg::PR => "pr",
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AArch64GeneralReg::X19 => "x19",
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AArch64GeneralReg::X20 => "x20",
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AArch64GeneralReg::X21 => "x21",
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AArch64GeneralReg::X22 => "x22",
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AArch64GeneralReg::X23 => "x23",
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AArch64GeneralReg::X24 => "x24",
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AArch64GeneralReg::X25 => "x25",
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AArch64GeneralReg::X26 => "x26",
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AArch64GeneralReg::X27 => "x27",
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AArch64GeneralReg::X28 => "x28",
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AArch64GeneralReg::FP => "fp",
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AArch64GeneralReg::LR => "lr",
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AArch64GeneralReg::ZRSP => "zrsp",
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}
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)
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write!(f, "{}", self.as_str_64bit())
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}
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}
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@ -1201,12 +1242,12 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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#[inline(always)]
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fn movsx_reg_reg(
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_buf: &mut Vec<'_, u8>,
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_input_width: RegisterWidth,
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_dst: AArch64GeneralReg,
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_src: AArch64GeneralReg,
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buf: &mut Vec<'_, u8>,
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input_width: RegisterWidth,
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dst: AArch64GeneralReg,
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src: AArch64GeneralReg,
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) {
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todo!("move with sign extension");
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sign_extend(buf, input_width, dst, src)
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}
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#[inline(always)]
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@ -1322,11 +1363,15 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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dst: AArch64GeneralReg,
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offset: i32,
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) {
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use RegisterWidth::*;
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// move to destination (zero extends)
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Self::mov_reg_base32(buf, register_width, dst, offset);
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// then sign-extend if needed
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match register_width {
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RegisterWidth::W8 => todo!("sign extend 1 byte values"),
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RegisterWidth::W16 => todo!("sign extend 2 byte values"),
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RegisterWidth::W32 => todo!("sign extend 4 byte values"),
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RegisterWidth::W64 => Self::mov_reg64_base32(buf, dst, offset),
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W8 | W16 | W32 => sign_extend(buf, register_width, dst, dst),
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W64 => { /* do nothing */ }
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}
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}
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@ -1337,11 +1382,15 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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dst: AArch64GeneralReg,
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offset: i32,
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) {
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use RegisterWidth::*;
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// move to destination (zero extends)
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Self::mov_reg_base32(buf, register_width, dst, offset);
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// then sign-extend if needed
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match register_width {
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RegisterWidth::W8 => todo!("zero extend 1 byte values"),
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RegisterWidth::W16 => todo!("zero extend 2 byte values"),
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RegisterWidth::W32 => todo!("zero extend 4 byte values"),
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RegisterWidth::W64 => Self::mov_reg64_base32(buf, dst, offset),
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W8 | W16 => zero_extend(buf, register_width, dst, dst),
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W32 | W64 => { /* do nothing */ }
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}
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}
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@ -2267,6 +2316,75 @@ impl UnconditionalBranchImmediate {
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}
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}
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#[derive(PackedStruct, Debug)]
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#[packed_struct(endian = "msb")]
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pub struct SignExtend {
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sf: Integer<u8, packed_bits::Bits<1>>,
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opc: Integer<u8, packed_bits::Bits<2>>,
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fixed: Integer<u8, packed_bits::Bits<6>>,
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n: Integer<u8, packed_bits::Bits<1>>,
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immr: Integer<u8, packed_bits::Bits<6>>,
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imms: Integer<u8, packed_bits::Bits<6>>,
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rn: Integer<u8, packed_bits::Bits<5>>,
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rd: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for SignExtend {}
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fn sign_extend(
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buf: &mut Vec<'_, u8>,
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register_width: RegisterWidth,
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dst: AArch64GeneralReg,
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src: AArch64GeneralReg,
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) {
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let imms = match register_width {
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RegisterWidth::W8 => 0b00_0111, // sxtb
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RegisterWidth::W16 => 0b00_1111, // sxth
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RegisterWidth::W32 => 0b01_1111, // sxtw
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RegisterWidth::W64 => return mov_reg64_reg64(buf, dst, src),
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};
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let inst = SignExtend {
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sf: 0b1.into(),
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opc: 0b00.into(),
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fixed: 0b100110.into(),
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n: 0b1.into(),
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immr: 0b00_0000.into(),
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imms: imms.into(),
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rn: src.id().into(),
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rd: dst.id().into(),
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};
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buf.extend(inst.bytes());
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}
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fn zero_extend(
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buf: &mut Vec<'_, u8>,
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register_width: RegisterWidth,
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dst: AArch64GeneralReg,
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src: AArch64GeneralReg,
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) {
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let imms = match register_width {
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RegisterWidth::W8 => 0b00_0111, // uxtb
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RegisterWidth::W16 => 0b00_1111, // uxth
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RegisterWidth::W32 => return mov_reg64_reg64(buf, dst, src),
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RegisterWidth::W64 => return mov_reg64_reg64(buf, dst, src),
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};
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let inst = SignExtend {
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sf: 0b0.into(),
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opc: 0b10.into(),
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fixed: 0b100110.into(),
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n: 0b0.into(),
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immr: 0b00_0000.into(),
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imms: imms.into(),
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rn: src.id().into(),
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rd: dst.id().into(),
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};
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buf.extend(inst.bytes());
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}
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// Uses unsigned Offset
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// opc = 0b01 means load
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// opc = 0b00 means store
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@ -3663,6 +3781,22 @@ mod tests {
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_ => format!("{self}"),
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}
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}
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fn capstone_string_32bit(&self, zrsp_kind: ZRSPKind) -> String {
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match self {
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AArch64GeneralReg::XR => "w8".to_owned(),
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AArch64GeneralReg::IP0 => "w16".to_owned(),
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AArch64GeneralReg::IP1 => "w17".to_owned(),
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AArch64GeneralReg::PR => "w18".to_owned(),
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AArch64GeneralReg::FP => "w29".to_owned(),
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AArch64GeneralReg::LR => "w30".to_owned(),
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AArch64GeneralReg::ZRSP => match zrsp_kind {
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UsesZR => "wzr".to_owned(),
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UsesSP => "sp".to_owned(),
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},
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_ => self.as_str_32bit().to_string(),
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}
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}
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}
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impl AArch64FloatReg {
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@ -3688,6 +3822,13 @@ mod tests {
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//const TEST_I32: i32 = 0x12345678;
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//const TEST_I64: i64 = 0x12345678_9ABCDEF0;
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const ALL_REGISTER_WIDTHS: &[RegisterWidth] = &[
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RegisterWidth::W8,
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RegisterWidth::W16,
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RegisterWidth::W32,
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RegisterWidth::W64,
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];
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const ALL_GENERAL_REGS: &[AArch64GeneralReg] = &[
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AArch64GeneralReg::X0,
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AArch64GeneralReg::X1,
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@ -4822,4 +4963,61 @@ mod tests {
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ALL_GENERAL_REGS
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);
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}
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#[test]
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fn test_sign_extend() {
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disassembler_test!(
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sign_extend,
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|w, reg1: AArch64GeneralReg, reg2: AArch64GeneralReg| format!(
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"{} {}, {}",
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match w {
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RegisterWidth::W8 => "sxtb",
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RegisterWidth::W16 => "sxth",
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RegisterWidth::W32 => "sxtw",
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RegisterWidth::W64 => "mov",
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},
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reg1.capstone_string(UsesZR),
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match w {
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RegisterWidth::W8 => reg2.capstone_string_32bit(UsesZR),
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RegisterWidth::W16 => reg2.capstone_string_32bit(UsesZR),
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RegisterWidth::W32 => reg2.capstone_string_32bit(UsesZR),
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RegisterWidth::W64 => reg2.capstone_string(UsesZR),
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}
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),
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ALL_REGISTER_WIDTHS,
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ALL_GENERAL_REGS,
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ALL_GENERAL_REGS
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);
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}
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#[test]
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fn test_zero_extend() {
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disassembler_test!(
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zero_extend,
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|w, reg1: AArch64GeneralReg, reg2: AArch64GeneralReg| format!(
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"{} {}, {}",
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match w {
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RegisterWidth::W8 => "uxtb",
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RegisterWidth::W16 => "uxth",
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RegisterWidth::W32 => "mov",
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RegisterWidth::W64 => "mov",
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},
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match w {
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RegisterWidth::W8 => reg1.capstone_string_32bit(UsesZR),
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RegisterWidth::W16 => reg1.capstone_string_32bit(UsesZR),
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RegisterWidth::W32 => reg1.capstone_string(UsesZR),
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RegisterWidth::W64 => reg1.capstone_string(UsesZR),
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},
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match w {
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RegisterWidth::W8 => reg2.capstone_string_32bit(UsesZR),
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RegisterWidth::W16 => reg2.capstone_string_32bit(UsesZR),
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RegisterWidth::W32 => reg2.capstone_string(UsesZR),
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RegisterWidth::W64 => reg2.capstone_string(UsesZR),
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}
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),
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ALL_REGISTER_WIDTHS,
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ALL_GENERAL_REGS,
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ALL_GENERAL_REGS
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);
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}
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}
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