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https://github.com/roc-lang/roc.git
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Add structs to make new method parameters more readable in aarch64
This commit is contained in:
Ajai Nelson
parent
260c080d41
commit
ca0ef8f88f
1 changed files with 332 additions and 73 deletions
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@ -1120,9 +1120,25 @@ pub struct MoveWideImmediate {
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impl Aarch64Bytes for MoveWideImmediate {}
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pub struct MoveWideImmediateParams {
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opc: u8,
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rd: AArch64GeneralReg,
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imm16: u16,
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hw: u8,
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sf: bool,
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}
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impl MoveWideImmediate {
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#[inline(always)]
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fn new(opc: u8, rd: AArch64GeneralReg, imm16: u16, hw: u8, sf: bool) -> Self {
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fn new(
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MoveWideImmediateParams {
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opc,
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rd,
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imm16,
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hw,
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sf,
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}: MoveWideImmediateParams,
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) -> Self {
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// TODO: revisit this is we change where we want to check the shift
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// currently this is done in the assembler above
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// assert!(shift % 16 == 0 && shift <= 48);
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@ -1155,15 +1171,26 @@ pub struct ArithmeticImmediate {
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impl Aarch64Bytes for ArithmeticImmediate {}
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pub struct ArithmeticImmediateParams {
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op: bool,
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s: bool,
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rd: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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imm12: u16,
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sh: bool,
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}
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impl ArithmeticImmediate {
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#[inline(always)]
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fn new(
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op: bool,
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s: bool,
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rd: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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imm12: u16,
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sh: bool,
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ArithmeticImmediateParams {
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op,
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s,
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rd,
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rn,
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imm12,
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sh,
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}: ArithmeticImmediateParams,
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) -> Self {
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debug_assert!(imm12 <= 0xFFF);
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@ -1215,16 +1242,28 @@ pub struct ArithmeticShifted {
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impl Aarch64Bytes for ArithmeticShifted {}
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pub struct ArithmeticShiftedParams {
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op: bool,
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s: bool,
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shift: ShiftType,
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imm6: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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}
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impl ArithmeticShifted {
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#[inline(always)]
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fn new(
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op: bool,
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s: bool,
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shift: ShiftType,
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imm6: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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ArithmeticShiftedParams {
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op,
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s,
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shift,
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imm6,
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rm,
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rn,
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rd,
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}: ArithmeticShiftedParams,
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) -> Self {
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debug_assert!(imm6 <= 0b111111);
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@ -1347,9 +1386,16 @@ pub struct ConditionalBranchImmediate {
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impl Aarch64Bytes for ConditionalBranchImmediate {}
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pub struct ConditionalBranchImmediateParams {
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cond: ConditionCode,
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imm19: u32,
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}
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impl ConditionalBranchImmediate {
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#[inline(always)]
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fn new(cond: ConditionCode, imm19: u32) -> Self {
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fn new(
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ConditionalBranchImmediateParams { cond, imm19 }: ConditionalBranchImmediateParams,
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) -> Self {
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debug_assert!(imm19 >> 19 == 0);
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Self {
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@ -1378,16 +1424,28 @@ pub struct ConditionalSelect {
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impl Aarch64Bytes for ConditionalSelect {}
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pub struct ConditionalSelectParams {
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op: bool,
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s: bool,
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cond: ConditionCode,
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op2: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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}
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impl ConditionalSelect {
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#[inline(always)]
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fn new(
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op: bool,
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s: bool,
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cond: ConditionCode,
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op2: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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ConditionalSelectParams {
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op,
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s,
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cond,
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op2,
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rm,
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rn,
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rd,
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}: ConditionalSelectParams,
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) -> Self {
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debug_assert!(op2 <= 0b11);
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@ -1422,9 +1480,18 @@ pub struct DataProcessingTwoSource {
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impl Aarch64Bytes for DataProcessingTwoSource {}
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pub struct DataProcessingTwoSourceParams {
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op: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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}
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impl DataProcessingTwoSource {
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#[inline(always)]
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fn new(op: u8, rm: AArch64GeneralReg, rn: AArch64GeneralReg, rd: AArch64GeneralReg) -> Self {
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fn new(
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DataProcessingTwoSourceParams { op, rm, rn, rd }: DataProcessingTwoSourceParams,
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) -> Self {
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debug_assert!(op <= 0b111111);
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Self {
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@ -1456,14 +1523,24 @@ pub struct DataProcessingThreeSource {
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impl Aarch64Bytes for DataProcessingThreeSource {}
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pub struct DataProcessingThreeSourceParams {
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op31: u8,
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rm: AArch64GeneralReg,
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ra: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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}
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impl DataProcessingThreeSource {
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#[inline(always)]
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fn new(
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op31: u8,
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rm: AArch64GeneralReg,
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ra: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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DataProcessingThreeSourceParams {
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op31,
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rm,
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ra,
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rn,
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rd,
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}: DataProcessingThreeSourceParams,
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) -> Self {
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debug_assert!(op31 <= 0b111);
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@ -1510,15 +1587,26 @@ pub struct LogicalShiftedRegister {
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impl Aarch64Bytes for LogicalShiftedRegister {}
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pub struct LogicalShiftedRegisterParams {
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op: LogicalOp,
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shift: ShiftType,
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imm6: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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}
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impl LogicalShiftedRegister {
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#[inline(always)]
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fn new(
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op: LogicalOp,
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shift: ShiftType,
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imm6: u8,
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rm: AArch64GeneralReg,
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rn: AArch64GeneralReg,
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rd: AArch64GeneralReg,
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LogicalShiftedRegisterParams {
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op,
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shift,
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imm6,
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rm,
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rn,
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rd,
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}: LogicalShiftedRegisterParams,
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) -> Self {
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debug_assert!(imm6 <= 0b111111);
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@ -1565,9 +1653,16 @@ pub struct UnconditionalBranchRegister {
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impl Aarch64Bytes for UnconditionalBranchRegister {}
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pub struct UnconditionalBranchRegisterParams {
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op: u8,
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rn: AArch64GeneralReg,
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}
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impl UnconditionalBranchRegister {
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#[inline(always)]
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fn new(op: u8, rn: AArch64GeneralReg) -> Self {
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fn new(
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UnconditionalBranchRegisterParams { op, rn }: UnconditionalBranchRegisterParams,
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) -> Self {
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debug_assert!(op <= 0b11);
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Self {
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@ -1595,9 +1690,16 @@ pub struct UnconditionalBranchImmediate {
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impl Aarch64Bytes for UnconditionalBranchImmediate {}
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pub struct UnconditionalBranchImmediateParams {
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op: bool,
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imm26: u32,
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}
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impl UnconditionalBranchImmediate {
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#[inline(always)]
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fn new(op: bool, imm26: u32) -> Self {
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fn new(
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UnconditionalBranchImmediateParams { op, imm26 }: UnconditionalBranchImmediateParams,
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) -> Self {
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debug_assert!(imm26 <= 0b11_1111_1111_1111_1111_1111_1111);
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Self {
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op,
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@ -1625,9 +1727,24 @@ pub struct LoadStoreRegisterImmediate {
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impl Aarch64Bytes for LoadStoreRegisterImmediate {}
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pub struct LoadStoreRegisterImmediateParams {
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size: u8,
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imm12: u16,
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rn: AArch64GeneralReg,
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rt: AArch64GeneralReg,
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}
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impl LoadStoreRegisterImmediate {
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#[inline(always)]
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fn new(size: u8, opc: u8, imm12: u16, rn: AArch64GeneralReg, rt: AArch64GeneralReg) -> Self {
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fn new(
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opc: u8,
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LoadStoreRegisterImmediateParams {
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size,
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imm12,
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rn,
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rt,
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}: LoadStoreRegisterImmediateParams,
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) -> Self {
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debug_assert!(size <= 0b11);
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debug_assert!(imm12 <= 0xFFF);
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@ -1644,13 +1761,13 @@ impl LoadStoreRegisterImmediate {
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}
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#[inline(always)]
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fn new_load(size: u8, imm12: u16, rn: AArch64GeneralReg, rt: AArch64GeneralReg) -> Self {
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Self::new(size, 0b01, imm12, rn, rt)
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fn new_load(params: LoadStoreRegisterImmediateParams) -> Self {
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Self::new(0b01, params)
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}
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#[inline(always)]
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fn new_store(size: u8, imm12: u16, rn: AArch64GeneralReg, rt: AArch64GeneralReg) -> Self {
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Self::new(size, 0b00, imm12, rn, rt)
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fn new_store(params: LoadStoreRegisterImmediateParams) -> Self {
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Self::new(0b00, params)
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}
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}
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@ -1668,7 +1785,14 @@ fn add_reg64_reg64_imm12(
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src: AArch64GeneralReg,
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imm12: u16,
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) {
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let inst = ArithmeticImmediate::new(false, false, dst, src, imm12, false);
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let inst = ArithmeticImmediate::new(ArithmeticImmediateParams {
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op: false,
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s: false,
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rd: dst,
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rn: src,
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imm12,
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sh: false,
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});
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buf.extend(inst.bytes());
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}
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@ -1681,7 +1805,15 @@ fn add_reg64_reg64_reg64(
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = ArithmeticShifted::new(false, false, ShiftType::LSL, 0, src2, src1, dst);
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let inst = ArithmeticShifted::new(ArithmeticShiftedParams {
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op: false,
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s: false,
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shift: ShiftType::LSL,
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imm6: 0,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1694,7 +1826,14 @@ fn and_reg64_reg64_reg64(
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = LogicalShiftedRegister::new(LogicalOp::AND, ShiftType::LSL, 0, src2, src1, dst);
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let inst = LogicalShiftedRegister::new(LogicalShiftedRegisterParams {
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op: LogicalOp::AND,
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shift: ShiftType::LSL,
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imm6: 0,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1707,7 +1846,12 @@ fn asr_reg64_reg64_reg64(
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001010, src2, src1, dst);
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let inst = DataProcessingTwoSource::new(DataProcessingTwoSourceParams {
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op: 0b001010,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1725,7 +1869,10 @@ fn b_cond_imm19(buf: &mut Vec<'_, u8>, cond: ConditionCode, imm19: i32) {
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debug_assert!(left_removed | 0b1111_1111_1111_1100_0000_0000_0000_0000 == unsigned);
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}
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let inst = ConditionalBranchImmediate::new(cond, left_removed);
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let inst = ConditionalBranchImmediate::new(ConditionalBranchImmediateParams {
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cond,
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imm19: left_removed,
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});
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buf.extend(inst.bytes());
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}
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@ -1743,7 +1890,10 @@ fn b_imm26(buf: &mut Vec<'_, u8>, imm26: i32) {
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debug_assert!(left_removed | 0b1111_1110_0000_0000_0000_0000_0000_0000 == unsigned);
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}
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let inst = UnconditionalBranchImmediate::new(false, left_removed);
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let inst = UnconditionalBranchImmediate::new(UnconditionalBranchImmediateParams {
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op: false,
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imm26: left_removed,
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});
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buf.extend(inst.bytes());
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}
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@ -1792,7 +1942,15 @@ fn csinc_reg64_reg64_reg64_cond(
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src2: AArch64GeneralReg,
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cond: ConditionCode,
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) {
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let inst = ConditionalSelect::new(false, false, cond, 0b01, src2, src1, dst);
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let inst = ConditionalSelect::new(ConditionalSelectParams {
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op: false,
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s: false,
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cond,
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op2: 0b01,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1806,7 +1964,15 @@ fn csneg_reg64_reg64_reg64_cond(
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src2: AArch64GeneralReg,
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cond: ConditionCode,
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) {
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let inst = ConditionalSelect::new(true, false, cond, 0b01, src2, src1, dst);
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let inst = ConditionalSelect::new(ConditionalSelectParams {
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op: true,
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s: false,
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cond,
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op2: 0b01,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1819,7 +1985,14 @@ fn eor_reg64_reg64_reg64(
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = LogicalShiftedRegister::new(LogicalOp::EOR, ShiftType::LSL, 0, src2, src1, dst);
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let inst = LogicalShiftedRegister::new(LogicalShiftedRegisterParams {
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op: LogicalOp::EOR,
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shift: ShiftType::LSL,
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imm6: 0,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1833,7 +2006,12 @@ fn ldr_reg64_reg64_imm12(
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base: AArch64GeneralReg,
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imm12: u16,
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) {
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let inst = LoadStoreRegisterImmediate::new_load(0b11, imm12, base, dst);
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let inst = LoadStoreRegisterImmediate::new_load(LoadStoreRegisterImmediateParams {
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size: 0b11,
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imm12,
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rn: base,
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rt: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1846,7 +2024,12 @@ fn lsl_reg64_reg64_reg64(
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001000, src2, src1, dst);
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let inst = DataProcessingTwoSource::new(DataProcessingTwoSourceParams {
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op: 0b001000,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1859,7 +2042,12 @@ fn lsr_reg64_reg64_reg64(
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001001, src2, src1, dst);
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let inst = DataProcessingTwoSource::new(DataProcessingTwoSourceParams {
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op: 0b001001,
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rm: src2,
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rn: src1,
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rd: dst,
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});
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buf.extend(inst.bytes());
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}
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@ -1873,7 +2061,13 @@ fn madd_reg64_reg64_reg64_reg64(
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src2: AArch64GeneralReg,
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src3: AArch64GeneralReg,
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) {
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let inst = DataProcessingThreeSource::new(0b000000, src2, src3, src1, dst);
|
||||
let inst = DataProcessingThreeSource::new(DataProcessingThreeSourceParams {
|
||||
op31: 0b000000,
|
||||
rm: src2,
|
||||
ra: src3,
|
||||
rn: src1,
|
||||
rd: dst,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1882,14 +2076,14 @@ fn madd_reg64_reg64_reg64_reg64(
|
|||
#[inline(always)]
|
||||
fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64GeneralReg) {
|
||||
// MOV is equvalent to `ORR Xd, XZR, XM` in AARCH64.
|
||||
let inst = LogicalShiftedRegister::new(
|
||||
LogicalOp::ORR,
|
||||
ShiftType::LSL,
|
||||
0,
|
||||
src,
|
||||
AArch64GeneralReg::ZRSP,
|
||||
dst,
|
||||
);
|
||||
let inst = LogicalShiftedRegister::new(LogicalShiftedRegisterParams {
|
||||
op: LogicalOp::ORR,
|
||||
shift: ShiftType::LSL,
|
||||
imm6: 0,
|
||||
rm: src,
|
||||
rn: AArch64GeneralReg::ZRSP,
|
||||
rd: dst,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1897,7 +2091,13 @@ fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64Ge
|
|||
/// `MOVK Xd, imm16` -> Keeps Xd and moves an optionally shifted imm16 to Xd.
|
||||
#[inline(always)]
|
||||
fn movk_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, hw: u8) {
|
||||
let inst = MoveWideImmediate::new(0b11, dst, imm16, hw, true);
|
||||
let inst = MoveWideImmediate::new(MoveWideImmediateParams {
|
||||
opc: 0b11,
|
||||
rd: dst,
|
||||
imm16,
|
||||
hw,
|
||||
sf: true,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1905,7 +2105,13 @@ fn movk_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, h
|
|||
/// `MOVZ Xd, imm16` -> Zeros Xd and moves an optionally shifted imm16 to Xd.
|
||||
#[inline(always)]
|
||||
fn movz_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, hw: u8) {
|
||||
let inst = MoveWideImmediate::new(0b10, dst, imm16, hw, true);
|
||||
let inst = MoveWideImmediate::new(MoveWideImmediateParams {
|
||||
opc: 0b10,
|
||||
rd: dst,
|
||||
imm16,
|
||||
hw,
|
||||
sf: true,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1935,7 +2141,14 @@ fn orr_reg64_reg64_reg64(
|
|||
src1: AArch64GeneralReg,
|
||||
src2: AArch64GeneralReg,
|
||||
) {
|
||||
let inst = LogicalShiftedRegister::new(LogicalOp::ORR, ShiftType::LSL, 0, src2, src1, dst);
|
||||
let inst = LogicalShiftedRegister::new(LogicalShiftedRegisterParams {
|
||||
op: LogicalOp::ORR,
|
||||
shift: ShiftType::LSL,
|
||||
imm6: 0,
|
||||
rm: src2,
|
||||
rn: src1,
|
||||
rd: dst,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1949,7 +2162,12 @@ fn sdiv_reg64_reg64_reg64(
|
|||
src1: AArch64GeneralReg,
|
||||
src2: AArch64GeneralReg,
|
||||
) {
|
||||
let inst = DataProcessingTwoSource::new(0b000011, src2, src1, dst);
|
||||
let inst = DataProcessingTwoSource::new(DataProcessingTwoSourceParams {
|
||||
op: 0b000011,
|
||||
rm: src2,
|
||||
rn: src1,
|
||||
rd: dst,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1963,7 +2181,12 @@ fn str_reg64_reg64_imm12(
|
|||
base: AArch64GeneralReg,
|
||||
imm12: u16,
|
||||
) {
|
||||
let inst = LoadStoreRegisterImmediate::new_store(0b11, imm12, base, src);
|
||||
let inst = LoadStoreRegisterImmediate::new_store(LoadStoreRegisterImmediateParams {
|
||||
size: 0b11,
|
||||
imm12,
|
||||
rn: base,
|
||||
rt: src,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1976,7 +2199,14 @@ fn sub_reg64_reg64_imm12(
|
|||
src: AArch64GeneralReg,
|
||||
imm12: u16,
|
||||
) {
|
||||
let inst = ArithmeticImmediate::new(true, false, dst, src, imm12, false);
|
||||
let inst = ArithmeticImmediate::new(ArithmeticImmediateParams {
|
||||
op: true,
|
||||
s: false,
|
||||
rd: dst,
|
||||
rn: src,
|
||||
imm12,
|
||||
sh: false,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -1989,7 +2219,15 @@ fn sub_reg64_reg64_reg64(
|
|||
src1: AArch64GeneralReg,
|
||||
src2: AArch64GeneralReg,
|
||||
) {
|
||||
let inst = ArithmeticShifted::new(true, false, ShiftType::LSL, 0, src2, src1, dst);
|
||||
let inst = ArithmeticShifted::new(ArithmeticShiftedParams {
|
||||
op: true,
|
||||
s: false,
|
||||
shift: ShiftType::LSL,
|
||||
imm6: 0,
|
||||
rm: src2,
|
||||
rn: src1,
|
||||
rd: dst,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -2002,7 +2240,14 @@ fn subs_reg64_reg64_imm12(
|
|||
src: AArch64GeneralReg,
|
||||
imm12: u16,
|
||||
) {
|
||||
let inst = ArithmeticImmediate::new(true, true, dst, src, imm12, false);
|
||||
let inst = ArithmeticImmediate::new(ArithmeticImmediateParams {
|
||||
op: true,
|
||||
s: true,
|
||||
rd: dst,
|
||||
rn: src,
|
||||
imm12,
|
||||
sh: false,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -2015,7 +2260,15 @@ fn subs_reg64_reg64_reg64(
|
|||
src1: AArch64GeneralReg,
|
||||
src2: AArch64GeneralReg,
|
||||
) {
|
||||
let inst = ArithmeticShifted::new(true, true, ShiftType::LSL, 0, src2, src1, dst);
|
||||
let inst = ArithmeticShifted::new(ArithmeticShiftedParams {
|
||||
op: true,
|
||||
s: true,
|
||||
shift: ShiftType::LSL,
|
||||
imm6: 0,
|
||||
rm: src2,
|
||||
rn: src1,
|
||||
rd: dst,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -2023,7 +2276,8 @@ fn subs_reg64_reg64_reg64(
|
|||
/// `RET Xn` -> Return to the address stored in Xn.
|
||||
#[inline(always)]
|
||||
fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) {
|
||||
let inst = UnconditionalBranchRegister::new(0b10, xn);
|
||||
let inst =
|
||||
UnconditionalBranchRegister::new(UnconditionalBranchRegisterParams { op: 0b10, rn: xn });
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
@ -2037,7 +2291,12 @@ fn udiv_reg64_reg64_reg64(
|
|||
src1: AArch64GeneralReg,
|
||||
src2: AArch64GeneralReg,
|
||||
) {
|
||||
let inst = DataProcessingTwoSource::new(0b000010, src2, src1, dst);
|
||||
let inst = DataProcessingTwoSource::new(DataProcessingTwoSourceParams {
|
||||
op: 0b000010,
|
||||
rm: src2,
|
||||
rn: src1,
|
||||
rd: dst,
|
||||
});
|
||||
|
||||
buf.extend(inst.bytes());
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue