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Add aarch64 instruction doc comments
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Ajai Nelson
parent
e39e434d20
commit
d30fdb9a8f
1 changed files with 55 additions and 16 deletions
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@ -987,7 +987,6 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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todo!("registers to float for AArch64");
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}
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// TODO: This next two are signed. Should they be?
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#[inline(always)]
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fn lte_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1256,20 +1255,35 @@ impl ArithmeticShifted {
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#[derive(Copy, Clone, PartialEq)]
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#[allow(dead_code)]
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enum ConditionCode {
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/// Equal
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EQ = 0b0000,
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/// Not equal
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NE = 0b0001,
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/// CS or HS: Carry set
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CSHS = 0b0010,
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/// CC or LO: Carry clear
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CCLO = 0b0011,
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/// Minus, negative
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MI = 0b0100,
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/// Plus, positive or zero
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PL = 0b0101,
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/// Overflow
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VS = 0b0110,
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/// No overflow
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VC = 0b0111,
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/// Unsigned higher
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HI = 0b1000,
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/// Unsigned lower or same
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LS = 0b1001,
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/// Signed greater than or equal
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GE = 0b1010,
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/// Signed less than
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LT = 0b1011,
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/// Signed greater than
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GT = 0b1100,
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/// Signed less than or equal
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LE = 0b1101,
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/// Always
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AL = 0b1110,
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}
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@ -1279,8 +1293,8 @@ impl ConditionCode {
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*self as u8
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}
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/// The inverse of the condition code. For example, EQ becomes NE.
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fn invert(self) -> Self {
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// TODO: check
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match self {
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ConditionCode::EQ => ConditionCode::NE,
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ConditionCode::NE => ConditionCode::EQ,
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@ -1678,6 +1692,7 @@ fn add_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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/// `AND Xd, Xn, Xm` -> Bitwise AND Xn and Xm and place the result into Xd.
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#[inline(always)]
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fn and_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1690,7 +1705,20 @@ fn and_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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/// TODO
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/// `ASR Xd, Xn, Xn` -> Arithmetic shift right Xn by Xm and place the result into Xd.
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#[inline(always)]
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fn asr_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001010, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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/// `B.cond imm19` -> Jump to PC + imm19 if cond is met.
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#[inline(always)]
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fn b_cond_imm19(buf: &mut Vec<'_, u8>, cond: ConditionCode, imm19: i32) {
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debug_assert!(imm19 & 0b11 == 0, "branch location must be 4-byte aligned");
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@ -1726,16 +1754,19 @@ fn b_imm26(buf: &mut Vec<'_, u8>, imm26: i32) {
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buf.extend(inst.bytes());
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}
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/// `CMP Xn, imm12` -> Compare Xn and imm12, setting condition flags.
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#[inline(always)]
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fn cmp_reg64_imm12(buf: &mut Vec<'_, u8>, src: AArch64GeneralReg, imm12: u16) {
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subs_reg64_reg64_imm12(buf, AArch64GeneralReg::ZRSP, src, imm12);
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}
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/// `CMP Xn, Xm` -> Compare Xn and Xm, setting condition flags.
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#[inline(always)]
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fn cmp_reg64_reg64(buf: &mut Vec<'_, u8>, src1: AArch64GeneralReg, src2: AArch64GeneralReg) {
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subs_reg64_reg64_reg64(buf, AArch64GeneralReg::ZRSP, src1, src2);
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}
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/// `CNEG Xd, Xn, cond` -> If cond is true, then Xd = -Xn, else Xd = Xn.
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#[inline(always)]
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fn cneg_reg64_reg64_cond(
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buf: &mut Vec<'_, u8>,
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@ -1746,6 +1777,7 @@ fn cneg_reg64_reg64_cond(
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csneg_reg64_reg64_reg64_cond(buf, dst, src, src, cond.invert());
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}
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/// `CSET Xd, cond` -> If cond is true, then Xd = 1, else Xd = 0.
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#[inline(always)]
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fn cset_reg64_cond(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, cond: ConditionCode) {
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csinc_reg64_reg64_reg64_cond(
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@ -1757,6 +1789,7 @@ fn cset_reg64_cond(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, cond: Conditio
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);
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}
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/// `CSINC Xd, Xn, Xm, cond` -> If cond is true, then Xd = Xn, else Xd = Xm + 1.
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#[inline(always)]
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fn csinc_reg64_reg64_reg64_cond(
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buf: &mut Vec<'_, u8>,
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@ -1770,6 +1803,7 @@ fn csinc_reg64_reg64_reg64_cond(
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buf.extend(inst.bytes());
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}
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/// `CSNEG Xd, Xn, Xm, cond` -> If cond is true, then Xd = Xn, else Xd = -Xm.
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#[inline(always)]
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fn csneg_reg64_reg64_reg64_cond(
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buf: &mut Vec<'_, u8>,
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@ -1783,6 +1817,7 @@ fn csneg_reg64_reg64_reg64_cond(
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buf.extend(inst.bytes());
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}
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/// `EOR Xd, Xn, Xm` -> Bitwise XOR Xn and Xm and place the result into Xd.
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#[inline(always)]
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fn eor_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1809,6 +1844,7 @@ fn ldr_reg64_reg64_imm12(
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buf.extend(inst.bytes());
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}
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/// `LSL Xd, Xn, Xm` -> Logical shift Xn left by Xm and place the result into Xd.
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#[inline(always)]
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fn lsl_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1821,6 +1857,7 @@ fn lsl_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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/// `LSR Xd, Xn, Xm` -> Logical shift Xn right by Xm and place the result into Xd.
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#[inline(always)]
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fn lsr_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1833,18 +1870,7 @@ fn lsr_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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#[inline(always)]
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fn asr_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: AArch64GeneralReg,
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src1: AArch64GeneralReg,
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src2: AArch64GeneralReg,
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) {
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let inst = DataProcessingTwoSource::new(0b001010, src2, src1, dst);
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buf.extend(inst.bytes());
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}
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/// `MADD Xd, Xn, Xm, Xa` -> Multiply Xn and Xm, add Xa, and place the result into Xd.
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#[inline(always)]
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fn madd_reg64_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1890,6 +1916,7 @@ fn movz_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, h
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buf.extend(inst.bytes());
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}
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/// `MUL Xd, Xn, Xm` -> Multiply Xn and Xm and place the result into Xd.
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#[inline(always)]
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fn mul_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1900,11 +1927,13 @@ fn mul_reg64_reg64_reg64(
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madd_reg64_reg64_reg64_reg64(buf, dst, src1, src2, AArch64GeneralReg::ZRSP);
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}
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/// `NEG Xd, Xm` -> Negate Xm and place the result into Xd.
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#[inline(always)]
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fn neg_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64GeneralReg) {
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sub_reg64_reg64_reg64(buf, dst, AArch64GeneralReg::ZRSP, src);
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}
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/// `ORR Xd, Xn, Xm` -> Bitwise OR Xn and Xm and place the result into Xd.
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#[inline(always)]
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fn orr_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1917,6 +1946,8 @@ fn orr_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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/// `SDIV Xd, Xn, Xm` -> Divide Xn by Xm and place the result into Xd.
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/// Xn, Xm, and Xd are signed integers.
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#[inline(always)]
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fn sdiv_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -1969,7 +2000,7 @@ fn sub_reg64_reg64_reg64(
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buf.extend(inst.bytes());
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}
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/// `SUBS Xd, Xn, imm12` ->
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/// `SUBS Xd, Xn, imm12` -> Subtract Xn and imm12 and place the result into Xd. Set condition flags.
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#[inline(always)]
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fn subs_reg64_reg64_imm12(
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buf: &mut Vec<'_, u8>,
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@ -1982,6 +2013,7 @@ fn subs_reg64_reg64_imm12(
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buf.extend(inst.bytes());
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}
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/// `SUBS Xd, Xn, Xm` -> Subtract Xn and Xm and place the result into Xd. Set condition flags.
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#[inline(always)]
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fn subs_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -2002,6 +2034,8 @@ fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) {
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buf.extend(inst.bytes());
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}
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/// `UDIV Xd, Xn, Xm` -> Divide Xn by Xm and place the result into Xd.
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/// Xn, Xm, and Xd are unsigned integers.
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#[inline(always)]
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fn udiv_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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@ -2114,6 +2148,11 @@ mod tests {
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(buf, cs)
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}
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// Many of these instructions are aliases for each other,
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// and depending on their arguments, they might get disassembled to a different instruction.
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// That's why we need `if` expressions in some of these tests.
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// The "alias conditions" for each instruction are listed in the ARM manual.
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#[test]
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fn test_add_reg64_reg64_reg64() {
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disassembler_test!(
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