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ranges
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e4ddc39b63
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1 changed files with 5 additions and 5 deletions
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@ -1403,7 +1403,7 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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) {
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if (-256..256).contains(&offset) {
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ldur_reg_reg_imm9(buf, register_width, dst, src, offset as i16);
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} else if (offset >> 3) <= 0xFFF {
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} else if (0..=u16::MAX as i32).contains(&offset) {
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debug_assert!(offset % 8 == 0);
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ldr_reg_reg_imm12(buf, register_width, dst, src, (offset as u16) >> 3);
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} else {
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@ -1461,7 +1461,7 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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) {
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if (-256..256).contains(&offset) {
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stur_reg_reg_imm9(buf, register_width, src, dst, offset as i16);
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} else if (offset >> 3) <= 0xFFF {
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} else if (0..=u16::MAX as i32).contains(&offset) {
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debug_assert_eq!(offset % 8, 0);
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str_reg_reg_imm12(buf, register_width, src, dst, (offset as u16) >> 3);
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} else {
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@ -1481,7 +1481,7 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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) {
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if offset < 0 {
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stur_freg64_reg64_imm9(buf, src, dst, offset as i16)
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} else if (offset >> 3) <= 0xFFF {
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} else if (0..=u16::MAX as i32).contains(&offset) {
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debug_assert!(offset % 8 == 0);
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str_freg64_reg64_imm12(buf, src, dst, (offset as u16) >> 3);
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} else {
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@ -1854,7 +1854,7 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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) {
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if offset < 0 {
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ldur_freg64_reg64_imm9(buf, dst, src, offset as i16)
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} else if (offset >> 3) <= 0xFFF {
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} else if (0..=u16::MAX as i32).contains(&offset) {
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debug_assert!(offset % 8 == 0);
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ldr_freg64_reg64_imm12(buf, dst, src, (offset as u16) >> 3);
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} else {
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@ -1870,7 +1870,7 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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) {
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if offset < 0 {
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ldur_freg64_reg64_imm9(buf, dst, src, offset as i16)
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} else if (offset >> 3) <= 0xFFF {
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} else if (0..=u16::MAX as i32).contains(&offset) {
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debug_assert!(offset % 8 == 0);
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ldr_freg64_reg64_imm12(buf, dst, src, (offset as u16) >> 3);
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} else {
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