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add x86_64 Int neq support for gen_dev
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parent
2eae1a857b
commit
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5 changed files with 134 additions and 1 deletions
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@ -490,6 +490,16 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
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unimplemented!("registers equality not implemented yet for AArch64");
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unimplemented!("registers equality not implemented yet for AArch64");
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}
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}
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#[inline(always)]
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fn neq_reg64_reg64_reg64(
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_buf: &mut Vec<'_, u8>,
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_dst: AArch64GeneralReg,
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_src1: AArch64GeneralReg,
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_src2: AArch64GeneralReg,
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) {
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unimplemented!("registers non-equality not implemented yet for AArch64");
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}
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#[inline(always)]
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#[inline(always)]
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fn ret(buf: &mut Vec<'_, u8>) {
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fn ret(buf: &mut Vec<'_, u8>) {
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ret_reg64(buf, AArch64GeneralReg::LR)
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ret_reg64(buf, AArch64GeneralReg::LR)
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@ -172,6 +172,13 @@ pub trait Assembler<GeneralReg: RegTrait, FloatReg: RegTrait> {
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src2: GeneralReg,
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src2: GeneralReg,
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);
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);
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fn neq_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: GeneralReg,
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src1: GeneralReg,
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src2: GeneralReg,
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);
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fn ret(buf: &mut Vec<'_, u8>);
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fn ret(buf: &mut Vec<'_, u8>);
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}
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}
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@ -842,6 +849,25 @@ impl<
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}
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}
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}
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}
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fn build_neq(
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&mut self,
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dst: &Symbol,
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src1: &Symbol,
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src2: &Symbol,
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arg_layout: &Layout<'a>,
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) -> Result<(), String> {
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match arg_layout {
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Layout::Builtin(Builtin::Int64) => {
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let dst_reg = self.claim_general_reg(dst)?;
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let src1_reg = self.load_to_general_reg(src1)?;
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let src2_reg = self.load_to_general_reg(src2)?;
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ASM::neq_reg64_reg64_reg64(&mut self.buf, dst_reg, src1_reg, src2_reg);
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Ok(())
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}
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x => Err(format!("NumNeq: layout, {:?}, not implemented yet", x)),
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}
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}
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fn create_struct(
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fn create_struct(
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&mut self,
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&mut self,
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sym: &Symbol,
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sym: &Symbol,
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@ -1096,6 +1096,17 @@ impl Assembler<X86_64GeneralReg, X86_64FloatReg> for X86_64Assembler {
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sete_reg64(buf, dst);
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sete_reg64(buf, dst);
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}
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}
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#[inline(always)]
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fn neq_reg64_reg64_reg64(
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buf: &mut Vec<'_, u8>,
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dst: X86_64GeneralReg,
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src1: X86_64GeneralReg,
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src2: X86_64GeneralReg,
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) {
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cmp_reg64_reg64(buf, src1, src2);
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setne_reg64(buf, dst);
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}
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#[inline(always)]
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#[inline(always)]
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fn ret(buf: &mut Vec<'_, u8>) {
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fn ret(buf: &mut Vec<'_, u8>) {
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ret(buf);
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ret(buf);
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@ -1475,6 +1486,26 @@ fn sete_reg64(buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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and_reg64_imm8(buf, reg, 1);
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and_reg64_imm8(buf, reg, 1);
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}
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}
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/// `SETNE r/m64` -> Set byte if not equal (ZF=0).
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#[inline(always)]
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fn setne_reg64(buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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// Follow `sete_reg64` implementation.
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// Change 94 => 95
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buf.reserve(7);
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let reg_mod = reg as u8 % 8;
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use X86_64GeneralReg::*;
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match reg {
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RAX | RCX | RDX | RBX => buf.extend(&[0x0F, 0x95, 0xC0 + reg_mod]),
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RSP | RBP | RSI | RDI => buf.extend(&[REX, 0x0F, 0x95, 0xC0 + reg_mod]),
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R8 | R9 | R10 | R11 | R12 | R13 | R14 | R15 => {
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buf.extend(&[REX + 1, 0x0F, 0x95, 0xC0 + reg_mod])
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}
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}
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and_reg64_imm8(buf, reg, 1);
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}
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/// `RET` -> Near return to calling procedure.
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/// `RET` -> Near return to calling procedure.
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#[inline(always)]
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#[inline(always)]
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fn ret(buf: &mut Vec<'_, u8>) {
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fn ret(buf: &mut Vec<'_, u8>) {
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@ -2074,6 +2105,46 @@ mod tests {
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}
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}
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}
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}
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#[test]
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// follow test_sete_reg64
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// refer it
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fn test_setne_reg64() {
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let arena = bumpalo::Bump::new();
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let mut buf = bumpalo::vec![in &arena];
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let (reg, expected) = (
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X86_64GeneralReg::RAX,
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[
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0x0F, 0x95, 0xC0, // SETNE al ;
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0x48, 0x83, 0xE0, 0x01,
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],
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);
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buf.clear();
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setne_reg64(&mut buf, reg);
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assert_eq!(expected, &buf[..]);
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for (reg, expected) in &[
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(
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X86_64GeneralReg::RSP,
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[
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// SETNE spl;
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0x40, 0x0F, 0x95, 0xC4, 0x48, 0x83, 0xE4, 0x01,
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],
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),
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(
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X86_64GeneralReg::R15,
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[
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// SETNE r15b;
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0x41, 0x0F, 0x95, 0xC7, 0x49, 0x83, 0xE7, 0x01,
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],
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),
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] {
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buf.clear();
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setne_reg64(&mut buf, *reg);
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assert_eq!(expected, &buf[..]);
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}
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}
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#[test]
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#[test]
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fn test_ret() {
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fn test_ret() {
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let arena = bumpalo::Bump::new();
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let arena = bumpalo::Bump::new();
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@ -416,6 +416,23 @@ where
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);
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);
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self.build_eq(sym, &args[0], &args[1], &arg_layouts[0])
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self.build_eq(sym, &args[0], &args[1], &arg_layouts[0])
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}
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}
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LowLevel::NotEq => {
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debug_assert_eq!(
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2,
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args.len(),
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"NotEq: expected to have exactly two argument"
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);
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debug_assert_eq!(
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arg_layouts[0], arg_layouts[1],
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"NotEq: expected all arguments of to have the same layout"
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);
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debug_assert_eq!(
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Layout::Builtin(Builtin::Int1),
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*ret_layout,
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"NotEq: expected to have return layout of type I1"
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);
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self.build_neq(sym, &args[0], &args[1], &arg_layouts[0])
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}
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LowLevel::NumRound => self.build_fn_call(
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LowLevel::NumRound => self.build_fn_call(
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sym,
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sym,
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bitcode::NUM_ROUND[FloatWidth::F64].to_string(),
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bitcode::NUM_ROUND[FloatWidth::F64].to_string(),
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@ -497,6 +514,15 @@ where
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arg_layout: &Layout<'a>,
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arg_layout: &Layout<'a>,
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) -> Result<(), String>;
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) -> Result<(), String>;
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/// build_neq stores the result of `src1 != src2` into dst.
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fn build_neq(
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&mut self,
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dst: &Symbol,
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src1: &Symbol,
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src2: &Symbol,
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arg_layout: &Layout<'a>,
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) -> Result<(), String>;
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/// literal_map gets the map from symbol to literal, used for lazy loading and literal folding.
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/// literal_map gets the map from symbol to literal, used for lazy loading and literal folding.
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fn literal_map(&mut self) -> &mut MutMap<Symbol, Literal<'a>>;
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fn literal_map(&mut self) -> &mut MutMap<Symbol, Literal<'a>>;
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@ -713,7 +713,7 @@ fn gen_int_eq() {
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}
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}
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#[test]
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#[test]
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#[cfg(any(feature = "gen-llvm", feature = "gen-wasm"))]
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#[cfg(any(feature = "gen-llvm", feature = "gen-wasm", feature = "gen-dev"))]
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fn gen_int_neq() {
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fn gen_int_neq() {
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assert_evals_to!(
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assert_evals_to!(
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indoc!(
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indoc!(
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