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https://github.com/roc-lang/roc.git
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feat: refactor byte reversal into triat helper and inline some thangs
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rvcas
parent
7f06d54816
commit
e4861b679d
1 changed files with 46 additions and 45 deletions
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@ -47,6 +47,7 @@ pub enum AArch64GeneralReg {
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impl RegTrait for AArch64GeneralReg {}
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impl AArch64GeneralReg {
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#[inline(always)]
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fn id(&self) -> u8 {
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*self as u8
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}
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@ -511,6 +512,21 @@ impl AArch64Assembler {}
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// https://developer.arm.com/documentation/ddi0487/ga
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// Map all instructions to a packed struct.
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trait Aarch64Bytes: PackedStruct {
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const N: usize = 4;
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#[inline(always)]
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fn bytes(&self) -> [u8; 4] {
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let mut bytes: [u8; 4] = [0, 0, 0, 0];
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self.pack_to_slice(&mut bytes).unwrap();
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bytes.reverse();
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bytes
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}
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}
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#[derive(PackedStruct, Debug)]
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#[packed_struct(endian = "msb")]
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pub struct MoveWideImmediate {
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@ -522,7 +538,10 @@ pub struct MoveWideImmediate {
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reg_d: Integer<u8, packed_bits::Bits<5>>, // AArch64GeneralReg
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}
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impl Aarch64Bytes for MoveWideImmediate {}
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impl MoveWideImmediate {
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#[inline(always)]
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fn new(opc: u8, rd: AArch64GeneralReg, imm16: u16, hw: u8, sf: bool) -> Self {
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// TODO: revisit this is we change where we want to check the shift
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// currently this is done in the assembler above
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@ -554,7 +573,10 @@ pub struct ArithmeticImmediate {
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reg_d: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for ArithmeticImmediate {}
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impl ArithmeticImmediate {
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#[inline(always)]
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fn new(
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op: bool,
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s: bool,
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@ -588,6 +610,7 @@ enum ShiftType {
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}
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impl ShiftType {
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#[inline(always)]
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fn id(&self) -> u8 {
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*self as u8
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}
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@ -608,7 +631,10 @@ pub struct ArithmeticShifted {
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reg_d: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for ArithmeticShifted {}
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impl ArithmeticShifted {
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#[inline(always)]
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fn new(
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op: bool,
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s: bool,
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@ -662,7 +688,10 @@ pub struct LogicalShiftedRegister {
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reg_d: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for LogicalShiftedRegister {}
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impl LogicalShiftedRegister {
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#[inline(always)]
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fn new(
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op: LogicalOp,
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shift: ShiftType,
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@ -712,7 +741,10 @@ pub struct UnconditionalBranchRegister {
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fixed5: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for UnconditionalBranchRegister {}
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impl UnconditionalBranchRegister {
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#[inline(always)]
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fn new(op: u8, rn: AArch64GeneralReg) -> Self {
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Self {
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fixed5: 0b00000.into(),
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@ -745,7 +777,10 @@ pub struct LoadStoreRegisterImmediate {
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rt: Integer<u8, packed_bits::Bits<5>>,
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}
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impl Aarch64Bytes for LoadStoreRegisterImmediate {}
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impl LoadStoreRegisterImmediate {
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#[inline(always)]
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fn new(size: u8, opc: u8, imm12: u16, rn: AArch64GeneralReg, rt: AArch64GeneralReg) -> Self {
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debug_assert!(size <= 0b11);
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debug_assert!(imm12 <= 0xFFF);
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@ -762,10 +797,12 @@ impl LoadStoreRegisterImmediate {
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}
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}
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#[inline(always)]
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fn new_load(size: u8, imm12: u16, rn: AArch64GeneralReg, rt: AArch64GeneralReg) -> Self {
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Self::new(size, 0b01, imm12, rn, rt)
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}
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#[inline(always)]
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fn new_store(size: u8, imm12: u16, rn: AArch64GeneralReg, rt: AArch64GeneralReg) -> Self {
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Self::new(size, 0b00, imm12, rn, rt)
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}
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@ -787,11 +824,7 @@ fn add_reg64_reg64_imm12(
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) {
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let inst = ArithmeticImmediate::new(false, false, dst, src, imm12, false);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `ADD Xd, Xm, Xn` -> Add Xm and Xn and place the result into Xd.
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@ -804,11 +837,7 @@ fn add_reg64_reg64_reg64(
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) {
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let inst = ArithmeticShifted::new(false, false, ShiftType::LSL, 0, src1, src2, dst);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `LDR Xt, [Xn, #offset]` -> Load Xn + Offset Xt. ZRSP is SP.
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@ -822,11 +851,7 @@ fn ldr_reg64_imm12(
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) {
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let inst = LoadStoreRegisterImmediate::new_load(0b11, imm12, base, dst);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `MOV Xd, Xm` -> Move Xm to Xd.
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@ -842,11 +867,7 @@ fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64Ge
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dst,
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);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `MOVK Xd, imm16` -> Keeps Xd and moves an optionally shifted imm16 to Xd.
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@ -854,11 +875,7 @@ fn mov_reg64_reg64(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, src: AArch64Ge
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fn movk_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, hw: u8) {
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let inst = MoveWideImmediate::new(0b11, dst, imm16, hw, true);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `MOVZ Xd, imm16` -> Zeros Xd and moves an optionally shifted imm16 to Xd.
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@ -866,11 +883,7 @@ fn movk_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, h
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fn movz_reg64_imm16(buf: &mut Vec<'_, u8>, dst: AArch64GeneralReg, imm16: u16, hw: u8) {
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let inst = MoveWideImmediate::new(0b10, dst, imm16, hw, true);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `STR Xt, [Xn, #offset]` -> Store Xt to Xn + Offset. ZRSP is SP.
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@ -884,11 +897,7 @@ fn str_reg64_imm12(
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) {
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let inst = LoadStoreRegisterImmediate::new_store(0b11, imm12, base, src);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `SUB Xd, Xn, imm12` -> Subtract Xn and imm12 and place the result into Xd.
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@ -901,11 +910,7 @@ fn sub_reg64_reg64_imm12(
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) {
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let inst = ArithmeticImmediate::new(true, false, dst, src, imm12, false);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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/// `RET Xn` -> Return to the address stored in Xn.
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@ -913,11 +918,7 @@ fn sub_reg64_reg64_imm12(
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fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) {
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let inst = UnconditionalBranchRegister::new(0b10, xn);
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let mut bytes = inst.pack().unwrap();
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bytes.reverse();
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buf.extend(bytes);
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buf.extend(inst.bytes());
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}
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#[cfg(test)]
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