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https://github.com/roc-lang/roc.git
synced 2025-07-24 06:55:15 +00:00
Replace addition with bitwise or
This commit is contained in:
Christoph Rüßler
parent
d409e5f93c
commit
ee4c62473e
1 changed files with 40 additions and 40 deletions
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@ -1264,12 +1264,12 @@ impl X86_64Assembler {
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}
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}
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const REX: u8 = 0x40;
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const REX_W: u8 = REX + 0x8;
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const REX_W: u8 = REX | 0x8;
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#[inline(always)]
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fn add_rm_extension<T: RegTrait>(reg: T, byte: u8) -> u8 {
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if reg.value() > 7 {
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byte + 1
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byte | 1
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} else {
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byte
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}
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@ -1283,7 +1283,7 @@ fn add_opcode_extension(reg: X86_64GeneralReg, byte: u8) -> u8 {
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#[inline(always)]
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fn add_reg_extension<T: RegTrait>(reg: T, byte: u8) -> u8 {
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if reg.value() > 7 {
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byte + 4
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byte | 4
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} else {
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byte
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}
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@ -1300,7 +1300,7 @@ fn binop_reg64_reg64(
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let rex = add_reg_extension(src, rex);
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let dst_mod = dst as u8 % 8;
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let src_mod = (src as u8 % 8) << 3;
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buf.extend(&[rex, op_code, 0xC0 + dst_mod + src_mod]);
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buf.extend(&[rex, op_code, 0xC0 | dst_mod | src_mod]);
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}
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#[inline(always)]
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@ -1315,7 +1315,7 @@ fn extended_binop_reg64_reg64(
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let rex = add_reg_extension(src, rex);
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let dst_mod = dst as u8 % 8;
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let src_mod = (src as u8 % 8) << 3;
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buf.extend(&[rex, op_code1, op_code2, 0xC0 + dst_mod + src_mod]);
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buf.extend(&[rex, op_code1, op_code2, 0xC0 | dst_mod | src_mod]);
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}
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// Below here are the functions for all of the assembly instructions.
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@ -1330,7 +1330,7 @@ fn add_reg64_imm32(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, imm: i32) {
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let rex = add_rm_extension(dst, REX_W);
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let dst_mod = dst as u8 % 8;
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buf.reserve(7);
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buf.extend(&[rex, 0x81, 0xC0 + dst_mod]);
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buf.extend(&[rex, 0x81, 0xC0 | dst_mod]);
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buf.extend(&imm.to_le_bytes());
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}
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@ -1350,13 +1350,13 @@ fn addsd_freg64_freg64(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, src: X86_64Fl
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if dst_high || src_high {
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buf.extend(&[
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0xF2,
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0x40 + ((dst_high as u8) << 2) + (src_high as u8),
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0x40 | ((dst_high as u8) << 2) | (src_high as u8),
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0x0F,
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0x58,
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0xC0 + (dst_mod << 3) + (src_mod),
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0xC0 | (dst_mod << 3) | (src_mod),
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])
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} else {
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buf.extend(&[0xF2, 0x0F, 0x58, 0xC0 + (dst_mod << 3) + (src_mod)])
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buf.extend(&[0xF2, 0x0F, 0x58, 0xC0 | (dst_mod << 3) | (src_mod)])
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}
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}
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@ -1370,13 +1370,13 @@ fn andpd_freg64_freg64(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, src: X86_64Fl
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if dst_high || src_high {
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buf.extend(&[
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0x66,
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0x40 + ((dst_high as u8) << 2) + (src_high as u8),
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0x40 | ((dst_high as u8) << 2) | (src_high as u8),
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0x0F,
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0x54,
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0xC0 + (dst_mod << 3) + (src_mod),
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0xC0 | (dst_mod << 3) | (src_mod),
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])
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} else {
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buf.extend(&[0x66, 0x0F, 0x54, 0xC0 + (dst_mod << 3) + (src_mod)])
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buf.extend(&[0x66, 0x0F, 0x54, 0xC0 | (dst_mod << 3) | (src_mod)])
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}
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}
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@ -1385,7 +1385,7 @@ fn andpd_freg64_freg64(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, src: X86_64Fl
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fn and_reg64_imm8(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, imm: i8) {
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let rex = add_rm_extension(dst, REX_W);
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let dst_mod = dst as u8 % 8;
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buf.extend(&[rex, 0x83, 0xE0 + dst_mod, imm as u8]);
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buf.extend(&[rex, 0x83, 0xE0 | dst_mod, imm as u8]);
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}
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/// `CMOVL r64,r/m64` -> Move if less (SF≠ OF).
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@ -1395,7 +1395,7 @@ fn cmovl_reg64_reg64(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, src: X86_64Ge
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let rex = add_rm_extension(src, rex);
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let dst_mod = (dst as u8 % 8) << 3;
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let src_mod = src as u8 % 8;
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buf.extend(&[rex, 0x0F, 0x4C, 0xC0 + dst_mod + src_mod]);
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buf.extend(&[rex, 0x0F, 0x4C, 0xC0 | dst_mod | src_mod]);
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}
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/// `CMP r/m64,i32` -> Compare i32 to r/m64.
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@ -1404,7 +1404,7 @@ fn cmp_reg64_imm32(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, imm: i32) {
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let rex = add_rm_extension(dst, REX_W);
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let dst_mod = dst as u8 % 8;
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buf.reserve(7);
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buf.extend(&[rex, 0x81, 0xF8 + dst_mod]);
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buf.extend(&[rex, 0x81, 0xF8 | dst_mod]);
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buf.extend(&imm.to_le_bytes());
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}
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@ -1452,7 +1452,7 @@ fn mov_reg64_imm32(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, imm: i32) {
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let rex = add_rm_extension(dst, REX_W);
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let dst_mod = dst as u8 % 8;
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buf.reserve(7);
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buf.extend(&[rex, 0xC7, 0xC0 + dst_mod]);
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buf.extend(&[rex, 0xC7, 0xC0 | dst_mod]);
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buf.extend(&imm.to_le_bytes());
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}
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@ -1465,7 +1465,7 @@ fn mov_reg64_imm64(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, imm: i64) {
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let rex = add_opcode_extension(dst, REX_W);
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let dst_mod = dst as u8 % 8;
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buf.reserve(10);
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buf.extend(&[rex, 0xB8 + dst_mod]);
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buf.extend(&[rex, 0xB8 | dst_mod]);
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buf.extend(&imm.to_le_bytes());
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}
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}
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@ -1501,7 +1501,7 @@ fn mov_base64_offset32_reg64(
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let src_mod = (src as u8 % 8) << 3;
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let base_mod = base as u8 % 8;
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buf.reserve(8);
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buf.extend(&[rex, 0x89, 0x80 + src_mod + base_mod]);
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buf.extend(&[rex, 0x89, 0x80 | src_mod | base_mod]);
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// Using RSP or R12 requires a secondary index byte.
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if base == X86_64GeneralReg::RSP || base == X86_64GeneralReg::R12 {
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buf.push(0x24);
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@ -1522,7 +1522,7 @@ fn mov_reg64_base64_offset32(
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let dst_mod = (dst as u8 % 8) << 3;
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let base_mod = base as u8 % 8;
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buf.reserve(8);
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buf.extend(&[rex, 0x8B, 0x80 + dst_mod + base_mod]);
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buf.extend(&[rex, 0x8B, 0x80 | dst_mod | base_mod]);
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// Using RSP or R12 requires a secondary index byte.
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if base == X86_64GeneralReg::RSP || base == X86_64GeneralReg::R12 {
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buf.push(0x24);
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@ -1543,7 +1543,7 @@ fn movzx_reg64_base8_offset32(
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let dst_mod = (dst as u8 % 8) << 3;
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let base_mod = base as u8 % 8;
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buf.reserve(9);
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buf.extend(&[rex, 0x0F, 0xB6, 0x80 + dst_mod + base_mod]);
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buf.extend(&[rex, 0x0F, 0xB6, 0x80 | dst_mod | base_mod]);
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// Using RSP or R12 requires a secondary index byte.
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if base == X86_64GeneralReg::RSP || base == X86_64GeneralReg::R12 {
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buf.push(0x24);
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@ -1571,13 +1571,13 @@ fn raw_movsd_freg64_freg64(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, src: X86_
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if dst_high || src_high {
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buf.extend(&[
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0xF2,
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0x40 + ((dst_high as u8) << 2) + (src_high as u8),
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0x40 | ((dst_high as u8) << 2) | (src_high as u8),
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0x0F,
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0x10,
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0xC0 + (dst_mod << 3) + (src_mod),
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0xC0 | (dst_mod << 3) | (src_mod),
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])
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} else {
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buf.extend(&[0xF2, 0x0F, 0x10, 0xC0 + (dst_mod << 3) + (src_mod)])
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buf.extend(&[0xF2, 0x0F, 0x10, 0xC0 | (dst_mod << 3) | (src_mod)])
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}
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}
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@ -1587,10 +1587,10 @@ fn movss_freg32_rip_offset32(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, offset:
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let dst_mod = dst as u8 % 8;
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if dst as u8 > 7 {
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buf.reserve(9);
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buf.extend(&[0xF3, 0x44, 0x0F, 0x10, 0x05 + (dst_mod << 3)]);
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buf.extend(&[0xF3, 0x44, 0x0F, 0x10, 0x05 | (dst_mod << 3)]);
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} else {
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buf.reserve(8);
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buf.extend(&[0xF3, 0x0F, 0x10, 0x05 + (dst_mod << 3)]);
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buf.extend(&[0xF3, 0x0F, 0x10, 0x05 | (dst_mod << 3)]);
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}
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buf.extend(&offset.to_le_bytes());
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}
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@ -1601,10 +1601,10 @@ fn movsd_freg64_rip_offset32(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, offset:
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let dst_mod = dst as u8 % 8;
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if dst as u8 > 7 {
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buf.reserve(9);
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buf.extend(&[0xF2, 0x44, 0x0F, 0x10, 0x05 + (dst_mod << 3)]);
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buf.extend(&[0xF2, 0x44, 0x0F, 0x10, 0x05 | (dst_mod << 3)]);
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} else {
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buf.reserve(8);
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buf.extend(&[0xF2, 0x0F, 0x10, 0x05 + (dst_mod << 3)]);
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buf.extend(&[0xF2, 0x0F, 0x10, 0x05 | (dst_mod << 3)]);
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}
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buf.extend(&offset.to_le_bytes());
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}
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@ -1626,7 +1626,7 @@ fn movsd_base64_offset32_freg64(
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if src as u8 > 7 || base as u8 > 7 {
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buf.push(rex);
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}
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buf.extend(&[0x0F, 0x11, 0x80 + src_mod + base_mod]);
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buf.extend(&[0x0F, 0x11, 0x80 | src_mod | base_mod]);
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// Using RSP or R12 requires a secondary index byte.
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if base == X86_64GeneralReg::RSP || base == X86_64GeneralReg::R12 {
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buf.push(0x24);
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@ -1651,7 +1651,7 @@ fn movsd_freg64_base64_offset32(
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if dst as u8 > 7 || base as u8 > 7 {
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buf.push(rex);
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}
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buf.extend(&[0x0F, 0x10, 0x80 + dst_mod + base_mod]);
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buf.extend(&[0x0F, 0x10, 0x80 | dst_mod | base_mod]);
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// Using RSP or R12 requires a secondary index byte.
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if base == X86_64GeneralReg::RSP || base == X86_64GeneralReg::R12 {
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buf.push(0x24);
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@ -1664,7 +1664,7 @@ fn movsd_freg64_base64_offset32(
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fn neg_reg64(buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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let rex = add_rm_extension(reg, REX_W);
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let reg_mod = reg as u8 % 8;
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buf.extend(&[rex, 0xF7, 0xD8 + reg_mod]);
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buf.extend(&[rex, 0xF7, 0xD8 | reg_mod]);
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}
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// helper function for `set*` instructions
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@ -1677,10 +1677,10 @@ fn set_reg64_help(op_code: u8, buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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let reg_mod = reg as u8 % 8;
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use X86_64GeneralReg::*;
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match reg {
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RAX | RCX | RDX | RBX => buf.extend(&[0x0F, op_code, 0xC0 + reg_mod]),
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RSP | RBP | RSI | RDI => buf.extend(&[REX, 0x0F, op_code, 0xC0 + reg_mod]),
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RAX | RCX | RDX | RBX => buf.extend(&[0x0F, op_code, 0xC0 | reg_mod]),
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RSP | RBP | RSI | RDI => buf.extend(&[REX, 0x0F, op_code, 0xC0 | reg_mod]),
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R8 | R9 | R10 | R11 | R12 | R13 | R14 | R15 => {
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buf.extend(&[REX + 1, 0x0F, op_code, 0xC0 + reg_mod])
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buf.extend(&[REX | 1, 0x0F, op_code, 0xC0 | reg_mod])
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}
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}
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@ -1702,7 +1702,7 @@ fn cvtsi2_help<T: RegTrait, U: RegTrait>(
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let mod1 = (dst.value() % 8) << 3;
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let mod2 = src.value() % 8;
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buf.extend(&[op_code1, rex, 0x0F, op_code2, 0xC0 + mod1 + mod2])
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buf.extend(&[op_code1, rex, 0x0F, op_code2, 0xC0 | mod1 | mod2])
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}
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#[inline(always)]
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@ -1716,7 +1716,7 @@ fn cvtsx2_help<T: RegTrait, V: RegTrait>(
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let mod1 = (dst.value() % 8) << 3;
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let mod2 = src.value() % 8;
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buf.extend(&[op_code1, 0x0F, op_code2, 0xC0 + mod1 + mod2])
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buf.extend(&[op_code1, 0x0F, op_code2, 0xC0 | mod1 | mod2])
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}
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/// `SETE r/m64` -> Set Byte on Condition - zero/equal (ZF=1)
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@ -1794,7 +1794,7 @@ fn sub_reg64_imm32(buf: &mut Vec<'_, u8>, dst: X86_64GeneralReg, imm: i32) {
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let rex = add_rm_extension(dst, REX_W);
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let dst_mod = dst as u8 % 8;
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buf.reserve(7);
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buf.extend(&[rex, 0x81, 0xE8 + dst_mod]);
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buf.extend(&[rex, 0x81, 0xE8 | dst_mod]);
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buf.extend(&imm.to_le_bytes());
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}
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@ -1810,9 +1810,9 @@ fn pop_reg64(buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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let reg_mod = reg as u8 % 8;
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if reg as u8 > 7 {
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let rex = add_opcode_extension(reg, REX);
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buf.extend(&[rex, 0x58 + reg_mod]);
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buf.extend(&[rex, 0x58 | reg_mod]);
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} else {
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buf.push(0x58 + reg_mod);
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buf.push(0x58 | reg_mod);
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}
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}
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@ -1822,9 +1822,9 @@ fn push_reg64(buf: &mut Vec<'_, u8>, reg: X86_64GeneralReg) {
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let reg_mod = reg as u8 % 8;
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if reg as u8 > 7 {
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let rex = add_opcode_extension(reg, REX);
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buf.extend(&[rex, 0x50 + reg_mod]);
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buf.extend(&[rex, 0x50 | reg_mod]);
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} else {
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buf.push(0x50 + reg_mod);
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buf.push(0x50 | reg_mod);
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}
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}
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