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auto clippy fixes

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This commit is contained in:
Folkert 2023-06-26 20:42:50 +02:00
parent 72c85efc83
commit ef39bad7c6
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GPG key ID: 1F17F6FFD112B97C
146 changed files with 750 additions and 1005 deletions
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2
crates/compiler/gen_dev/src/generic64/aarch64.rs
View file

@ -3164,7 +3164,7 @@ mod tests {
UsesZR => "xzr".to_owned(),
UsesSP => "sp".to_owned(),
},
_ => format!("{}", self),
_ => format!("{self}"),
}
}
}

86
crates/compiler/gen_dev/src/generic64/x86_64.rs
View file

@ -3612,7 +3612,7 @@ mod tests {
fn test_add_reg64_imm32() {
disassembler_test!(
add_reg64_imm32,
|reg, imm| format!("add {}, 0x{:x}", reg, imm),
|reg, imm| format!("add {reg}, 0x{imm:x}"),
ALL_GENERAL_REGS,
[TEST_I32]
);
@ -3622,7 +3622,7 @@ mod tests {
fn test_add_reg64_reg64() {
disassembler_test!(
add_reg64_reg64,
|reg1, reg2| format!("add {}, {}", reg1, reg2),
|reg1, reg2| format!("add {reg1}, {reg2}"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
@ -3632,7 +3632,7 @@ mod tests {
fn test_sub_reg64_reg64() {
disassembler_test!(
sub_reg64_reg64,
|reg1, reg2| format!("sub {}, {}", reg1, reg2),
|reg1, reg2| format!("sub {reg1}, {reg2}"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
@ -3642,7 +3642,7 @@ mod tests {
fn test_addsd_freg64_freg64() {
disassembler_test!(
addsd_freg64_freg64,
|reg1, reg2| format!("addsd {}, {}", reg1, reg2),
|reg1, reg2| format!("addsd {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -3652,7 +3652,7 @@ mod tests {
fn test_addss_freg32_freg32() {
disassembler_test!(
addss_freg32_freg32,
|reg1, reg2| format!("addss {}, {}", reg1, reg2),
|reg1, reg2| format!("addss {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -3662,7 +3662,7 @@ mod tests {
fn test_andpd_freg64_freg64() {
disassembler_test!(
andpd_freg64_freg64,
|reg1, reg2| format!("andpd {}, {}", reg1, reg2),
|reg1, reg2| format!("andpd {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -3729,7 +3729,7 @@ mod tests {
fn test_cmovl_reg64_reg64() {
disassembler_test!(
cmovl_reg64_reg64,
|reg1, reg2| format!("cmovl {}, {}", reg1, reg2),
|reg1, reg2| format!("cmovl {reg1}, {reg2}"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
@ -3739,7 +3739,7 @@ mod tests {
fn test_cmp_reg64_imm32() {
disassembler_test!(
cmp_reg64_imm32,
|reg, imm| format!("cmp {}, 0x{:x}", reg, imm),
|reg, imm| format!("cmp {reg}, 0x{imm:x}"),
ALL_GENERAL_REGS,
[TEST_I32]
);
@ -3749,7 +3749,7 @@ mod tests {
fn test_imul_reg64_reg64() {
disassembler_test!(
imul_reg64_reg64,
|reg1, reg2| format!("imul {}, {}", reg1, reg2),
|reg1, reg2| format!("imul {reg1}, {reg2}"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
@ -3759,7 +3759,7 @@ mod tests {
fn test_mul_reg64_reg64() {
disassembler_test!(
mul_reg64_reg64,
|reg| format!("mul {}", reg),
|reg| format!("mul {reg}"),
ALL_GENERAL_REGS
);
}
@ -3768,7 +3768,7 @@ mod tests {
fn test_mulsd_freg64_freg64() {
disassembler_test!(
mulsd_freg64_freg64,
|reg1, reg2| format!("mulsd {}, {}", reg1, reg2),
|reg1, reg2| format!("mulsd {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -3778,7 +3778,7 @@ mod tests {
fn test_mulss_freg32_freg32() {
disassembler_test!(
mulss_freg32_freg32,
|reg1, reg2| format!("mulss {}, {}", reg1, reg2),
|reg1, reg2| format!("mulss {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -3788,7 +3788,7 @@ mod tests {
fn test_idiv_reg64_reg64() {
disassembler_test!(
idiv_reg64_reg64,
|reg| format!("cqo\nidiv {}", reg),
|reg| format!("cqo\nidiv {reg}"),
ALL_GENERAL_REGS
);
}
@ -3797,7 +3797,7 @@ mod tests {
fn test_div_reg64_reg64() {
disassembler_test!(
udiv_reg64_reg64,
|reg| format!("cqo\ndiv {}", reg),
|reg| format!("cqo\ndiv {reg}"),
ALL_GENERAL_REGS
);
}
@ -3806,7 +3806,7 @@ mod tests {
fn test_divsd_freg64_freg64() {
disassembler_test!(
divsd_freg64_freg64,
|reg1, reg2| format!("divsd {}, {}", reg1, reg2),
|reg1, reg2| format!("divsd {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -3816,7 +3816,7 @@ mod tests {
fn test_divss_freg32_freg32() {
disassembler_test!(
divss_freg32_freg32,
|reg1, reg2| format!("divss {}, {}", reg1, reg2),
|reg1, reg2| format!("divss {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -3846,7 +3846,7 @@ mod tests {
fn test_mov_reg64_imm32() {
disassembler_test!(
mov_reg64_imm32,
|reg, imm| format!("mov {}, 0x{:x}", reg, imm),
|reg, imm| format!("mov {reg}, 0x{imm:x}"),
ALL_GENERAL_REGS,
[TEST_I32]
);
@ -3856,13 +3856,13 @@ mod tests {
fn test_mov_reg64_imm64() {
disassembler_test!(
mov_reg64_imm64,
|reg, imm| format!("movabs {}, 0x{:x}", reg, imm),
|reg, imm| format!("movabs {reg}, 0x{imm:x}"),
ALL_GENERAL_REGS,
[TEST_I64]
);
disassembler_test!(
mov_reg64_imm64,
|reg, imm| format!("mov {}, 0x{:x}", reg, imm),
|reg, imm| format!("mov {reg}, 0x{imm:x}"),
ALL_GENERAL_REGS,
[TEST_I32 as i64]
);
@ -3872,7 +3872,7 @@ mod tests {
fn test_lea_reg64() {
disassembler_test!(
lea_reg64,
|reg| format!("lea {}, [rip]", reg),
|reg| format!("lea {reg}, [rip]"),
ALL_GENERAL_REGS
);
}
@ -3898,7 +3898,7 @@ mod tests {
X86_64GeneralReg::low_32bits_string(&reg1),
X86_64GeneralReg::low_32bits_string(&reg2)
),
RegisterWidth::W64 => format!("mov {}, {}", reg1, reg2),
RegisterWidth::W64 => format!("mov {reg1}, {reg2}"),
}
},
ALL_REGISTER_WIDTHS,
@ -3967,7 +3967,7 @@ mod tests {
fn test_movsd_freg64_base64_offset32() {
disassembler_test!(
movsd_freg64_base64_offset32,
|reg1, reg2, imm| format!("movsd {}, qword ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("movsd {reg1}, qword ptr [{reg2} + 0x{imm:x}]"),
ALL_FLOAT_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -3978,7 +3978,7 @@ mod tests {
fn test_movss_freg32_base32_offset32() {
disassembler_test!(
movss_freg32_base32_offset32,
|reg1, reg2, imm| format!("movss {}, dword ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("movss {reg1}, dword ptr [{reg2} + 0x{imm:x}]"),
ALL_FLOAT_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -3989,7 +3989,7 @@ mod tests {
fn test_movsd_base64_offset32_freg64() {
disassembler_test!(
movsd_base64_offset32_freg64,
|reg1, imm, reg2| format!("movsd qword ptr [{} + 0x{:x}], {}", reg1, imm, reg2),
|reg1, imm, reg2| format!("movsd qword ptr [{reg1} + 0x{imm:x}], {reg2}"),
ALL_GENERAL_REGS,
[TEST_I32],
ALL_FLOAT_REGS
@ -4011,7 +4011,7 @@ mod tests {
fn test_mov_reg64_base64_offset32() {
disassembler_test!(
mov_reg64_base64_offset32,
|reg1, reg2, imm| format!("mov {}, qword ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("mov {reg1}, qword ptr [{reg2} + 0x{imm:x}]"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -4070,7 +4070,7 @@ mod tests {
fn test_mov_base64_offset32_reg64() {
disassembler_test!(
mov_base64_offset32_reg64,
|reg1, imm, reg2| format!("mov qword ptr [{} + 0x{:x}], {}", reg1, imm, reg2),
|reg1, imm, reg2| format!("mov qword ptr [{reg1} + 0x{imm:x}], {reg2}"),
ALL_GENERAL_REGS,
[TEST_I32],
ALL_GENERAL_REGS
@ -4129,7 +4129,7 @@ mod tests {
fn test_movsx_reg64_base32_offset32() {
disassembler_test!(
movsx_reg64_base32_offset32,
|reg1, reg2, imm| format!("movsxd {}, dword ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("movsxd {reg1}, dword ptr [{reg2} + 0x{imm:x}]"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -4140,7 +4140,7 @@ mod tests {
fn test_movsx_reg64_base16_offset32() {
disassembler_test!(
movsx_reg64_base16_offset32,
|reg1, reg2, imm| format!("movsx {}, word ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("movsx {reg1}, word ptr [{reg2} + 0x{imm:x}]"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -4151,7 +4151,7 @@ mod tests {
fn test_movsx_reg64_base8_offset32() {
disassembler_test!(
movsx_reg64_base8_offset32,
|reg1, reg2, imm| format!("movsx {}, byte ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("movsx {reg1}, byte ptr [{reg2} + 0x{imm:x}]"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -4162,7 +4162,7 @@ mod tests {
fn test_movzx_reg64_base16_offset32() {
disassembler_test!(
movzx_reg64_base16_offset32,
|reg1, reg2, imm| format!("movzx {}, word ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("movzx {reg1}, word ptr [{reg2} + 0x{imm:x}]"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -4173,7 +4173,7 @@ mod tests {
fn test_movzx_reg64_base8_offset32() {
disassembler_test!(
movzx_reg64_base8_offset32,
|reg1, reg2, imm| format!("movzx {}, byte ptr [{} + 0x{:x}]", reg1, reg2, imm),
|reg1, reg2, imm| format!("movzx {reg1}, byte ptr [{reg2} + 0x{imm:x}]"),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
[TEST_I32]
@ -4194,7 +4194,7 @@ mod tests {
fn test_movq_reg64_freg64() {
disassembler_test!(
movq_reg64_freg64,
|dst, src| format!("movq {}, {}", dst, src),
|dst, src| format!("movq {dst}, {src}"),
ALL_GENERAL_REGS,
ALL_FLOAT_REGS
);
@ -4204,7 +4204,7 @@ mod tests {
fn test_movsd_freg64_freg64() {
disassembler_test!(
raw_movsd_freg64_freg64,
|reg1, reg2| format!("movsd {}, {}", reg1, reg2),
|reg1, reg2| format!("movsd {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -4214,7 +4214,7 @@ mod tests {
fn test_movss_freg32_freg32() {
disassembler_test!(
raw_movss_freg32_freg32,
|reg1, reg2| format!("movss {}, {}", reg1, reg2),
|reg1, reg2| format!("movss {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -4224,7 +4224,7 @@ mod tests {
fn test_movss_freg32_rip_offset32() {
disassembler_test!(
movss_freg32_rip_offset32,
|reg, imm| format!("movss {}, dword ptr [rip + 0x{:x}]", reg, imm),
|reg, imm| format!("movss {reg}, dword ptr [rip + 0x{imm:x}]"),
ALL_FLOAT_REGS,
[TEST_I32 as u32]
);
@ -4234,7 +4234,7 @@ mod tests {
fn test_movsd_freg64_rip_offset32() {
disassembler_test!(
movsd_freg64_rip_offset32,
|reg, imm| format!("movsd {}, qword ptr [rip + 0x{:x}]", reg, imm),
|reg, imm| format!("movsd {reg}, qword ptr [rip + 0x{imm:x}]"),
ALL_FLOAT_REGS,
[TEST_I32 as u32]
);
@ -4242,7 +4242,7 @@ mod tests {
#[test]
fn test_neg_reg64() {
disassembler_test!(neg_reg64, |reg| format!("neg {}", reg), ALL_GENERAL_REGS);
disassembler_test!(neg_reg64, |reg| format!("neg {reg}"), ALL_GENERAL_REGS);
}
#[test]
@ -4251,13 +4251,13 @@ mod tests {
const CVTTSS2SI_CODE: u8 = 0x2C;
disassembler_test!(
|buf, r1, r2| cvtsi2_help(buf, 0xF3, CVTSI2SS_CODE, r1, r2),
|reg1, reg2| format!("cvtsi2ss {}, {}", reg1, reg2),
|reg1, reg2| format!("cvtsi2ss {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_GENERAL_REGS
);
disassembler_test!(
|buf, r1, r2| cvtsi2_help(buf, 0xF3, CVTTSS2SI_CODE, r1, r2),
|reg1, reg2| format!("cvttss2si {}, {}", reg1, reg2),
|reg1, reg2| format!("cvttss2si {reg1}, {reg2}"),
ALL_GENERAL_REGS,
ALL_FLOAT_REGS
);
@ -4268,7 +4268,7 @@ mod tests {
const CVTSS2SD_CODE: u8 = 0x5A;
disassembler_test!(
|buf, r1, r2| cvtsi2_help(buf, 0xF3, CVTSS2SD_CODE, r1, r2),
|reg1, reg2| format!("cvtss2sd {}, {}", reg1, reg2),
|reg1, reg2| format!("cvtss2sd {reg1}, {reg2}"),
ALL_FLOAT_REGS,
ALL_FLOAT_REGS
);
@ -4292,7 +4292,7 @@ mod tests {
fn test_sub_reg64_imm32() {
disassembler_test!(
sub_reg64_imm32,
|reg, imm| format!("sub {}, 0x{:x}", reg, imm),
|reg, imm| format!("sub {reg}, 0x{imm:x}"),
ALL_GENERAL_REGS,
[TEST_I32]
);
@ -4300,12 +4300,12 @@ mod tests {
#[test]
fn test_pop_reg64() {
disassembler_test!(pop_reg64, |reg| format!("pop {}", reg), ALL_GENERAL_REGS);
disassembler_test!(pop_reg64, |reg| format!("pop {reg}"), ALL_GENERAL_REGS);
}
#[test]
fn test_push_reg64() {
disassembler_test!(push_reg64, |reg| format!("push {}", reg), ALL_GENERAL_REGS);
disassembler_test!(push_reg64, |reg| format!("push {reg}"), ALL_GENERAL_REGS);
}
#[test]

2
crates/compiler/gen_dev/src/lib.rs
View file

@ -351,7 +351,7 @@ trait Backend<'a> {
// the functions from the generates #help module (refcounting, equality) is always suffixed
// with 1. That is fine, they are always unique anyway.
if ident_string.contains("#help") {
format!("{}_{}_1", module_string, ident_string)
format!("{module_string}_{ident_string}_1")
} else {
format!("{}_{}_{}", module_string, ident_string, state.finish())
}

2
crates/compiler/gen_dev/src/object_builder.rs
View file

@ -605,7 +605,7 @@ fn build_proc<'a, B: Backend<'a>>(
let elfreloc = match reloc {
Relocation::LocalData { offset, data } => {
let data_symbol = write::Symbol {
name: format!("{}.data{}", fn_name, local_data_index)
name: format!("{fn_name}.data{local_data_index}")
.as_bytes()
.to_vec(),
value: 0,