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Add cmp_reg64_reg64 instruction for aarch64

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Ajai Nelson 2023-03-22 02:34:42 -04:00
parent 003e3560ec
commit f7443812ca
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1 changed files with 67 additions and 0 deletions
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67
crates/compiler/gen_dev/src/generic64/aarch64.rs
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@ -1676,6 +1676,11 @@ fn cmp_reg64_imm12(buf: &mut Vec<'_, u8>, src: AArch64GeneralReg, imm12: u16) {
subs_reg64_reg64_imm12(buf, AArch64GeneralReg::ZRSP, src, imm12); subs_reg64_reg64_imm12(buf, AArch64GeneralReg::ZRSP, src, imm12);
} }
#[inline(always)]
fn cmp_reg64_reg64(buf: &mut Vec<'_, u8>, src1: AArch64GeneralReg, src2: AArch64GeneralReg) {
subs_reg64_reg64_reg64(buf, AArch64GeneralReg::ZRSP, src1, src2);
}
#[inline(always)] #[inline(always)]
fn cneg_reg64_reg64_cond( fn cneg_reg64_reg64_cond(
buf: &mut Vec<'_, u8>, buf: &mut Vec<'_, u8>,
@ -1887,6 +1892,18 @@ fn subs_reg64_reg64_imm12(
buf.extend(inst.bytes()); buf.extend(inst.bytes());
} }
#[inline(always)]
fn subs_reg64_reg64_reg64(
buf: &mut Vec<'_, u8>,
dst: AArch64GeneralReg,
src1: AArch64GeneralReg,
src2: AArch64GeneralReg,
) {
let inst = ArithmeticShifted::new(true, true, ShiftType::LSL, 0, src2, src1, dst);
buf.extend(inst.bytes());
}
/// `RET Xn` -> Return to the address stored in Xn. /// `RET Xn` -> Return to the address stored in Xn.
#[inline(always)] #[inline(always)]
fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) { fn ret_reg64(buf: &mut Vec<'_, u8>, xn: AArch64GeneralReg) {
@ -2073,6 +2090,20 @@ mod tests {
[0x123] [0x123]
); );
} }
#[test]
fn test_cmp_reg64_reg64() {
disassembler_test!(
cmp_reg64_reg64,
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg| format!(
"cmp {}, {}",
reg1.capstone_string(UsesZR),
reg2.capstone_string(UsesZR)
),
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
}
#[test] #[test]
fn test_cneg_reg64_reg64_cond() { fn test_cneg_reg64_reg64_cond() {
@ -2433,6 +2464,42 @@ mod tests {
[0x123] [0x123]
); );
} }
#[test]
fn test_subs_reg64_reg64_reg64() {
disassembler_test!(
subs_reg64_reg64_reg64,
|reg1: AArch64GeneralReg, reg2: AArch64GeneralReg, reg3: AArch64GeneralReg| {
if reg1 == AArch64GeneralReg::ZRSP {
// When the first register is SP, it gets disassembled as cmp,
// which is an alias for subs.
format!(
"cmp {}, {}",
reg2.capstone_string(UsesZR),
reg3.capstone_string(UsesZR)
)
} else if reg2 == AArch64GeneralReg::ZRSP {
// When the second register is ZR, it gets disassembled as negs,
// which is an alias for subs.
format!(
"negs {}, {}",
reg1.capstone_string(UsesZR),
reg3.capstone_string(UsesZR)
)
} else {
format!(
"subs {}, {}, {}",
reg1.capstone_string(UsesZR),
reg2.capstone_string(UsesZR),
reg3.capstone_string(UsesZR)
)
}
},
ALL_GENERAL_REGS,
ALL_GENERAL_REGS,
ALL_GENERAL_REGS
);
}
#[test] #[test]
fn test_ret_reg64() { fn test_ret_reg64() {