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load/store from any float register

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Folkert 2023-09-15 19:25:55 +02:00
parent 1becbbd61b
commit f9c53fc237
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GPG key ID: 1F17F6FFD112B97C
3 changed files with 39 additions and 12 deletions
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35
crates/compiler/gen_dev/src/generic64/aarch64.rs
View file

@ -1252,12 +1252,12 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
todo!()
}
#[inline(always)]
fn mov_base32_freg64(_buf: &mut Vec<'_, u8>, _offset: i32, _src: AArch64FloatReg) {
todo!("saving floating point reg to base offset for AArch64");
fn mov_base32_freg64(buf: &mut Vec<'_, u8>, offset: i32, src: AArch64FloatReg) {
Self::mov_mem64_offset32_freg64(buf, AArch64GeneralReg::FP, offset, src)
}
#[inline(always)]
fn mov_base32_freg32(_buf: &mut Vec<'_, u8>, _offset: i32, _src: AArch64FloatReg) {
todo!("saving floating point reg to base offset for AArch64");
fn mov_base32_freg32(buf: &mut Vec<'_, u8>, offset: i32, src: AArch64FloatReg) {
Self::mov_mem64_offset32_freg64(buf, AArch64GeneralReg::FP, offset, src)
}
#[inline(always)]
fn movesd_mem64_offset32_freg64(
@ -1362,6 +1362,23 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
}
}
#[inline(always)]
fn mov_mem64_offset32_freg64(
buf: &mut Vec<'_, u8>,
dst: AArch64GeneralReg,
offset: i32,
src: AArch64FloatReg,
) {
if offset < 0 {
todo!("negative mem offsets for AArch64");
} else if offset < (0xFFF << 8) {
debug_assert!(offset % 8 == 0);
str_freg64_reg64_imm12(buf, src, dst, (offset as u16) >> 3);
} else {
todo!("mem offsets over 32k for AArch64");
}
}
#[inline(always)]
fn mov_mem32_offset32_reg32(
_buf: &mut Vec<'_, u8>,
@ -1439,15 +1456,9 @@ impl Assembler<AArch64GeneralReg, AArch64FloatReg> for AArch64Assembler {
}
#[inline(always)]
fn mov_stack32_freg64(buf: &mut Vec<'_, u8>, offset: i32, src: AArch64FloatReg) {
if offset < 0 {
todo!("negative stack offsets for AArch64");
} else if offset < (0xFFF << 8) {
debug_assert!(offset % 8 == 0);
str_freg64_reg64_imm12(buf, src, AArch64GeneralReg::ZRSP, (offset as u16) >> 3);
} else {
todo!("stack offsets over 32k for AArch64");
}
Self::mov_mem64_offset32_freg64(buf, AArch64GeneralReg::ZRSP, offset, src)
}
#[inline(always)]
fn mov_stack32_reg(
buf: &mut Vec<'_, u8>,

6
crates/compiler/gen_dev/src/generic64/mod.rs
View file

@ -420,6 +420,12 @@ pub trait Assembler<GeneralReg: RegTrait, FloatReg: RegTrait>: Sized + Copy {
offset: i32,
);
fn mov_mem64_offset32_freg64(
buf: &mut Vec<'_, u8>,
dst: GeneralReg,
offset: i32,
src: FloatReg,
);
fn mov_freg64_stack32(buf: &mut Vec<'_, u8>, dst: FloatReg, offset: i32);
fn mov_reg64_stack32(buf: &mut Vec<'_, u8>, dst: GeneralReg, offset: i32);
fn mov_stack32_freg64(buf: &mut Vec<'_, u8>, offset: i32, src: FloatReg);

10
crates/compiler/gen_dev/src/generic64/x86_64.rs
View file

@ -2422,6 +2422,16 @@ impl Assembler<X86_64GeneralReg, X86_64FloatReg> for X86_64Assembler {
}
}
#[inline(always)]
fn mov_mem64_offset32_freg64(
buf: &mut Vec<'_, u8>,
dst: X86_64GeneralReg,
offset: i32,
src: X86_64FloatReg,
) {
movsd_base64_offset32_freg64(buf, dst, offset, src)
}
#[inline(always)]
fn mov_freg64_stack32(buf: &mut Vec<'_, u8>, dst: X86_64FloatReg, offset: i32) {
movsd_freg64_base64_offset32(buf, dst, X86_64GeneralReg::RSP, offset)