9 commits

Author	SHA1	Message	Date
Richard Feldman	fb5f30e5ed	Rename Arm to Aarch32, fix some of its code gen ... As far as I can tell, Aarch32 only supports 32-bit registers, so its pointers should be 4 bytes and its F64 alignment should be 4 bytes as well (because it's emulated in software).	2022-05-24 12:08:08 -04:00
Richard Feldman	2a5e6ab172	Add PartialEq, Eq, and EnumIter to Architecture	2022-05-24 12:08:07 -04:00
Richard Feldman	c685acd3cd	Derive Eq for PtrWidth	2022-05-20 23:36:54 -04:00
Richard Feldman	f6b1d3b592	Add TargetInfo::ptr_size	2022-05-20 23:36:54 -04:00
Anton-4	0f59f3097a	cargo fix --edition	2022-05-16 17:04:17 +02:00
Richard Feldman	e272a720aa	Add ptr_alignment_bytes	2022-05-07 10:20:40 -04:00
Richard Feldman	57b7832917	Upgrade target-lexicon	2022-04-23 20:51:57 -04:00
Brendan Hansknecht	dff1255fd3	properly get target_info and move claim stack fully to storage manager	2022-02-17 14:47:24 -08:00
Folkert	afd11e1cb1	move target -> roc_target	2022-01-26 23:33:29 +01:00