Richard Feldman fb5f30e5ed Rename Arm to Aarch32, fix some of its code gen ... As far as I can tell, Aarch32 only supports 32-bit registers, so its pointers should be 4 bytes and its F64 alignment should be 4 bytes as well (because it's emulated in software).		2022-05-24 12:08:08 -04:00
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bitcode.rs	Rename Arm to Aarch32, fix some of its code gen	2022-05-24 12:08:08 -04:00
lib.rs	rename standard_library -> roc	2022-03-23 21:19:15 +01:00
roc.rs	Add JSON builtin, pass along solved specializations per module	2022-05-19 18:21:40 -04:00
std.rs	Update to use new square brace formatting	2022-05-22 23:15:54 -04:00