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Fix typo
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dalance 2025-05-21 14:52:57 +09:00
parent 09437280b3
commit 3a804d7b3c
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1 changed files with 3 additions and 3 deletions
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6
crates/std/veryl/src/slicer/slicer.veryl
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@ -5,7 +5,7 @@ pub module slicer #(
param ASCENDING_ORDER: bool = true ,
param FULL_BANDWIDTH : bool = true ,
param DISABLE_MBFF : bool = false ,
param UES_RESET : bool = false ,
param USE_RESET : bool = false ,
) (
i_clk : input clock,
i_rst : input reset,
@ -36,7 +36,7 @@ pub module slicer #(
}
for i in 0..STAGES :g {
const RESET: bool = UES_RESET && (i == (STAGES - 1));
const RESET: bool = USE_RESET && (i == (STAGES - 1));
if FULL_BANDWIDTH :g {
inst u_slicer: slicer_unit_fb #(
@ -84,7 +84,7 @@ pub module slicer #(
}
for i in 0..STAGES :g {
const RESET: bool = UES_RESET && (i == 0);
const RESET: bool = USE_RESET && (i == 0);
if FULL_BANDWIDTH :g {
inst u_slicer: slicer_unit_fb #(