Taichi Ishitani
|
c740049cba
|
check use of unsigned loop variable in descending order for loop
(refs: veryl-lang/veryl#1808)
|
2025-07-25 16:04:25 +09:00 |
|
Taichi Ishitani
|
35b7be59b5
|
support for loop in descending order
(refs: veryl-lang/veryl#1779)
|
2025-07-24 09:38:32 +09:00 |
|
Taichi Ishitani
|
af15440744
|
support omittable RHS value of proto param
(refs: veryl-lang/veryl#1770)
|
2025-07-16 10:13:55 +09:00 |
|
Taichi Ishitani
|
ec3e9bf8b7
|
fix issue that prefix/suffix are not added to clock/reset signal in expression identifier
(refs: veryl-lang/veryl#1786)
|
2025-07-15 16:30:48 +09:00 |
|
dalance
|
9c0de98948
|
Fix compile error in testcase
|
2025-07-08 17:21:02 +09:00 |
|
Taichi Ishitani
|
8d269425ed
|
fix panic on function call in proto module declaration
(refs: veryl-lang/veryl#1760)
|
2025-07-08 16:30:42 +09:00 |
|
Taichi Ishitani
|
b210f31872
|
fix issue that formatter removes RHS of proto typedef
(refs: veryl-lang/veryl#1761)
|
2025-07-08 00:49:59 +09:00 |
|
Taichi Ishitani
|
71951a01ab
|
fix case that prefix/suffix are not added to clock/reset ports
(refs: veryl-lang/veryl#1756)
|
2025-07-07 09:26:58 +09:00 |
|
Taichi Ishitani
|
a33d52e782
|
fix wrong emitting location of import delcarations
(refs: veryl-lang/veryl#1758)
|
2025-07-07 00:39:23 +09:00 |
|
Taichi Ishitani
|
bd8dbf5f86
|
add components referenced only as alias target to filelist
(refs: veryl-lang/veryl#1748)
|
2025-07-01 15:15:02 +09:00 |
|
Taichi Ishitani
|
a00a72ec5b
|
move import declarations to component header
(refs: veryl-lang/veryl#1735)
|
2025-06-27 17:00:51 +09:00 |
|
Taichi Ishitani
|
19443dde33
|
support embed declaration in component declaration
(refs: veryl-lang/veryl#1698)
|
2025-06-18 10:15:00 +09:00 |
|
Taichi Ishitani
|
3e1b8c2a31
|
fix wrong filelist order
(refs: veryl-lang/veryl#1716)
|
2025-06-17 16:01:01 +09:00 |
|
Taichi Ishitani
|
6f2a15fd9e
|
replace proto package with actual package during resolving import
(refs: veryl-lang/veryl#1703, veryl-lang/veryl#1706)
|
2025-06-17 13:11:15 +09:00 |
|
Taichi Ishitani
|
1f9eecc93e
|
insert type dag edge between base and actual generic arg
(refs: veryl-lang/veryl#1657)
|
2025-05-22 23:59:41 +09:00 |
|
dalance
|
564dad64db
|
Remove case item indent
|
2025-05-20 16:52:01 +09:00 |
|
Taichi Ishitani
|
1bf72f198f
|
fix wrong collection of modport default members
(refs: veryl-lang/veryl#1639)
|
2025-05-18 22:08:26 +09:00 |
|
Taichi Ishitani
|
ad752a321a
|
wrap connect statement with begin/end block
(refs: veryl-lang/veryl#1637)
|
2025-05-18 14:57:04 +09:00 |
|
Taichi Ishitani
|
3e9276d188
|
fix emittion of alias generic interface
(refs: veryl-lang/veryl#1638)
|
2025-05-17 23:05:19 +09:00 |
|
Taichi Ishitani
|
02b3e75378
|
fix emission of function args of which type is modport
(refs: veryl-lang/veryl#1627)
|
2025-05-16 11:56:56 +09:00 |
|
Taichi Ishitani
|
a7787e696f
|
add a build option to shorten mangled name
(refs: veryl-lang/veryl#1608)
|
2025-05-15 08:27:00 +09:00 |
|
Taichi Ishitani
|
60c4de4de3
|
fix width calcuration for width-less based number literal
(refs: veryl-lang/veryl#1583)
|
2025-05-04 18:47:39 +09:00 |
|
dalance
|
01471da7ba
|
Forbid last item with ifdef in comma-separated list
|
2025-05-03 09:30:50 +09:00 |
|
Taichi Ishitani
|
ee82cebcb8
|
remove '$' character from project prefix of std lib
(refs: veryl-lang/veryl#1574)
|
2025-05-02 21:05:06 +09:00 |
|
Taichi Ishitani
|
444c378127
|
allow to use modport as function argument
(refs: veryl-lang/veryl#961)
|
2025-04-30 09:30:27 +09:00 |
|
Taichi Ishitani
|
10d64466b2
|
remove const generic boundary
|
2025-04-29 08:42:50 +09:00 |
|
Taichi Ishitani
|
bf886f7ee9
|
support typed proto generic boundary
(refs: veryl-lang/veryl#1533)
|
2025-04-29 08:42:50 +09:00 |
|
Taichi Ishitani
|
4c3a3dc79d
|
introduce u8, u16, i8 and i16 fixed types
(refs: veryl-lang/veryl#1536)
|
2025-04-18 17:10:56 +09:00 |
|
dalance
|
86648188d1
|
Trace member of generic parameter type
|
2025-04-18 15:43:18 +09:00 |
|
Taichi Ishitani
|
5022c6dfdf
|
introduce interface prototype
(refs: veryl-lang/veryl#963)
|
2025-04-16 17:21:18 +09:00 |
|
Taichi Ishitani
|
781b17b38a
|
insert cast to enum variant value
(refs: veryl-lang/veryl#1480)
|
2025-04-11 16:07:34 +09:00 |
|
dalance
|
b691bae7fa
|
Change clock domain annotation symbol to '
|
2025-04-11 15:14:06 +09:00 |
|
Taichi Ishitani
|
82a238d94c
|
implement modport expansion
(refs: veryl-lang/veryl#1246)
|
2025-04-11 10:45:42 +09:00 |
|
dalance
|
62632fcb0c
|
Keep directory hierarchy for target = {type = "directory"}
|
2025-04-09 19:18:46 +09:00 |
|
dalance
|
2db46915ef
|
Fix align after multi-line items
|
2025-04-09 11:51:59 +09:00 |
|
Taichi Ishitani
|
91ae3c809c
|
rename els attribute with else
|
2025-04-05 11:41:32 +09:00 |
|
dalance
|
1c12d7f427
|
Fix unexpected emission of #[els]
|
2025-04-04 17:05:02 +09:00 |
|
dalance
|
55e3f87e87
|
Fix panic at expression in package
|
2025-04-04 16:43:24 +09:00 |
|
dalance
|
b5fd0d562d
|
Add elsif/els attribute
|
2025-04-04 12:14:55 +09:00 |
|
Taichi Ishitani
|
2f8b8c9766
|
introduce proto alias declaration
(refs: veryl-lang/veryl#1459)
|
2025-04-04 10:17:43 +09:00 |
|
dalance
|
89dcdd850b
|
Fix unexpected error by reset value initialized by function
|
2025-04-02 18:03:31 +09:00 |
|
Taichi Ishitani
|
1256e2459e
|
simplify if expression notation
(refs: veryl-lang/veryl#1445)
|
2025-03-30 00:18:31 +09:00 |
|
dalance
|
cc455bb5f6
|
UndefinedIdentifierFunction call with named argument suppor0
|
2025-03-29 08:49:35 +09:00 |
|
Taichi Ishitani
|
66b26721d3
|
introduce connect operation
(refs: veryl-lang/veryl#1399, veryl-lang/veryl#1391)
|
2025-03-27 16:26:49 +09:00 |
|
dalance
|
b32b80b124
|
Multi-line case item support
|
2025-03-27 10:29:13 +09:00 |
|
dalance
|
a84ff33576
|
Change dependency syntax
|
2025-03-24 10:57:02 +09:00 |
|
dalance
|
c6b39a5cce
|
Struct constructor support
|
2025-03-24 10:32:09 +09:00 |
|
dalance
|
4ce0d0e1d2
|
Fix unexpected output of SystemVerilog modport
|
2025-03-21 19:08:10 +09:00 |
|
dalance
|
857860c5eb
|
Fix unexpected failure at SystemVerilog interface member
|
2025-03-21 17:30:28 +09:00 |
|
Taichi Ishitani
|
65e77f5a89
|
introduce bool type
(refs: veryl-lang/veryl#110)
|
2025-03-14 18:08:40 +09:00 |
|