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gh-109693: Remove pycore_atomic.h (gh-110992)
This commit is contained in:
Donghee Na
GitHub
parent
232465204e
commit
2dcc57008b
8 changed files with 4 additions and 564 deletions
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@ -1,557 +0,0 @@
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#ifndef Py_INTERNAL_ATOMIC_H
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#define Py_INTERNAL_ATOMIC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef Py_BUILD_CORE
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# error "this header requires Py_BUILD_CORE define"
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#endif
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#include "pyconfig.h" // HAVE_STD_ATOMIC
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#include "dynamic_annotations.h" // _Py_ANNOTATE_MEMORY_ORDER
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#ifdef HAVE_STD_ATOMIC
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# include <stdatomic.h> // atomic_store_explicit()
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#endif
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#if defined(_MSC_VER)
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# include <intrin.h> // _InterlockedExchange64()
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# if defined(_M_IX86) || defined(_M_X64)
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# include <immintrin.h> // _InterlockedExchange_HLEAcquire()
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# endif
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#endif
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/* This is modeled after the atomics interface from C1x, according to
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* the draft at
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* http://www.open-std.org/JTC1/SC22/wg14/www/docs/n1425.pdf.
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* Operations and types are named the same except with a _Py_ prefix
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* and have the same semantics.
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*
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* Beware, the implementations here are deep magic.
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*/
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#if defined(HAVE_STD_ATOMIC)
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typedef enum _Py_memory_order {
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_Py_memory_order_relaxed = memory_order_relaxed,
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_Py_memory_order_acquire = memory_order_acquire,
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_Py_memory_order_release = memory_order_release,
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_Py_memory_order_acq_rel = memory_order_acq_rel,
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_Py_memory_order_seq_cst = memory_order_seq_cst
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} _Py_memory_order;
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typedef struct _Py_atomic_address {
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atomic_uintptr_t _value;
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} _Py_atomic_address;
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typedef struct _Py_atomic_int {
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atomic_int _value;
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} _Py_atomic_int;
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#define _Py_atomic_signal_fence(/*memory_order*/ ORDER) \
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atomic_signal_fence(ORDER)
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#define _Py_atomic_thread_fence(/*memory_order*/ ORDER) \
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atomic_thread_fence(ORDER)
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#define _Py_atomic_store_explicit(ATOMIC_VAL, NEW_VAL, ORDER) \
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atomic_store_explicit(&((ATOMIC_VAL)->_value), NEW_VAL, ORDER)
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#define _Py_atomic_load_explicit(ATOMIC_VAL, ORDER) \
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atomic_load_explicit(&((ATOMIC_VAL)->_value), ORDER)
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// Use builtin atomic operations in GCC >= 4.7 and clang
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#elif defined(HAVE_BUILTIN_ATOMIC)
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typedef enum _Py_memory_order {
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_Py_memory_order_relaxed = __ATOMIC_RELAXED,
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_Py_memory_order_acquire = __ATOMIC_ACQUIRE,
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_Py_memory_order_release = __ATOMIC_RELEASE,
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_Py_memory_order_acq_rel = __ATOMIC_ACQ_REL,
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_Py_memory_order_seq_cst = __ATOMIC_SEQ_CST
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} _Py_memory_order;
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typedef struct _Py_atomic_address {
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uintptr_t _value;
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} _Py_atomic_address;
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typedef struct _Py_atomic_int {
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int _value;
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} _Py_atomic_int;
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#define _Py_atomic_signal_fence(/*memory_order*/ ORDER) \
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__atomic_signal_fence(ORDER)
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#define _Py_atomic_thread_fence(/*memory_order*/ ORDER) \
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__atomic_thread_fence(ORDER)
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#define _Py_atomic_store_explicit(ATOMIC_VAL, NEW_VAL, ORDER) \
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(assert((ORDER) == __ATOMIC_RELAXED \
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|| (ORDER) == __ATOMIC_SEQ_CST \
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|| (ORDER) == __ATOMIC_RELEASE), \
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__atomic_store_n(&((ATOMIC_VAL)->_value), NEW_VAL, ORDER))
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#define _Py_atomic_load_explicit(ATOMIC_VAL, ORDER) \
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(assert((ORDER) == __ATOMIC_RELAXED \
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|| (ORDER) == __ATOMIC_SEQ_CST \
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|| (ORDER) == __ATOMIC_ACQUIRE \
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|| (ORDER) == __ATOMIC_CONSUME), \
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__atomic_load_n(&((ATOMIC_VAL)->_value), ORDER))
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/* Only support GCC (for expression statements) and x86 (for simple
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* atomic semantics) and MSVC x86/x64/ARM */
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#elif defined(__GNUC__) && (defined(__i386__) || defined(__amd64))
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typedef enum _Py_memory_order {
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_Py_memory_order_relaxed,
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_Py_memory_order_acquire,
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_Py_memory_order_release,
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_Py_memory_order_acq_rel,
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_Py_memory_order_seq_cst
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} _Py_memory_order;
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typedef struct _Py_atomic_address {
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uintptr_t _value;
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} _Py_atomic_address;
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typedef struct _Py_atomic_int {
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int _value;
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} _Py_atomic_int;
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static __inline__ void
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_Py_atomic_signal_fence(_Py_memory_order order)
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{
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if (order != _Py_memory_order_relaxed)
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__asm__ volatile("":::"memory");
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}
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static __inline__ void
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_Py_atomic_thread_fence(_Py_memory_order order)
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{
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if (order != _Py_memory_order_relaxed)
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__asm__ volatile("mfence":::"memory");
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}
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/* Tell the race checker about this operation's effects. */
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static __inline__ void
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_Py_ANNOTATE_MEMORY_ORDER(const volatile void *address, _Py_memory_order order)
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{
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(void)address; /* shut up -Wunused-parameter */
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switch(order) {
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case _Py_memory_order_release:
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case _Py_memory_order_acq_rel:
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case _Py_memory_order_seq_cst:
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_Py_ANNOTATE_HAPPENS_BEFORE(address);
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break;
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case _Py_memory_order_relaxed:
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case _Py_memory_order_acquire:
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break;
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}
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switch(order) {
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case _Py_memory_order_acquire:
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case _Py_memory_order_acq_rel:
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case _Py_memory_order_seq_cst:
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_Py_ANNOTATE_HAPPENS_AFTER(address);
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break;
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case _Py_memory_order_relaxed:
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case _Py_memory_order_release:
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break;
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}
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}
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#define _Py_atomic_store_explicit(ATOMIC_VAL, NEW_VAL, ORDER) \
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__extension__ ({ \
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__typeof__(ATOMIC_VAL) atomic_val = ATOMIC_VAL; \
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__typeof__(atomic_val->_value) new_val = NEW_VAL;\
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volatile __typeof__(new_val) *volatile_data = &atomic_val->_value; \
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_Py_memory_order order = ORDER; \
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_Py_ANNOTATE_MEMORY_ORDER(atomic_val, order); \
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\
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/* Perform the operation. */ \
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_Py_ANNOTATE_IGNORE_WRITES_BEGIN(); \
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switch(order) { \
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case _Py_memory_order_release: \
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_Py_atomic_signal_fence(_Py_memory_order_release); \
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/* fallthrough */ \
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case _Py_memory_order_relaxed: \
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*volatile_data = new_val; \
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break; \
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\
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case _Py_memory_order_acquire: \
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case _Py_memory_order_acq_rel: \
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case _Py_memory_order_seq_cst: \
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__asm__ volatile("xchg %0, %1" \
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: "+r"(new_val) \
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: "m"(atomic_val->_value) \
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: "memory"); \
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break; \
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} \
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_Py_ANNOTATE_IGNORE_WRITES_END(); \
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})
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#define _Py_atomic_load_explicit(ATOMIC_VAL, ORDER) \
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__extension__ ({ \
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__typeof__(ATOMIC_VAL) atomic_val = ATOMIC_VAL; \
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__typeof__(atomic_val->_value) result; \
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volatile __typeof__(result) *volatile_data = &atomic_val->_value; \
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_Py_memory_order order = ORDER; \
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_Py_ANNOTATE_MEMORY_ORDER(atomic_val, order); \
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\
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/* Perform the operation. */ \
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_Py_ANNOTATE_IGNORE_READS_BEGIN(); \
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switch(order) { \
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case _Py_memory_order_release: \
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case _Py_memory_order_acq_rel: \
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case _Py_memory_order_seq_cst: \
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/* Loads on x86 are not releases by default, so need a */ \
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/* thread fence. */ \
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_Py_atomic_thread_fence(_Py_memory_order_release); \
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break; \
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default: \
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/* No fence */ \
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break; \
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} \
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result = *volatile_data; \
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switch(order) { \
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case _Py_memory_order_acquire: \
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case _Py_memory_order_acq_rel: \
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case _Py_memory_order_seq_cst: \
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/* Loads on x86 are automatically acquire operations so */ \
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/* can get by with just a compiler fence. */ \
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_Py_atomic_signal_fence(_Py_memory_order_acquire); \
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break; \
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default: \
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/* No fence */ \
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break; \
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} \
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_Py_ANNOTATE_IGNORE_READS_END(); \
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result; \
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})
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#elif defined(_MSC_VER)
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/* _Interlocked* functions provide a full memory barrier and are therefore
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enough for acq_rel and seq_cst. If the HLE variants aren't available
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in hardware they will fall back to a full memory barrier as well.
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This might affect performance but likely only in some very specific and
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hard to measure scenario.
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*/
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#if defined(_M_IX86) || defined(_M_X64)
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typedef enum _Py_memory_order {
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_Py_memory_order_relaxed,
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_Py_memory_order_acquire,
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_Py_memory_order_release,
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_Py_memory_order_acq_rel,
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_Py_memory_order_seq_cst
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} _Py_memory_order;
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typedef struct _Py_atomic_address {
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volatile uintptr_t _value;
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} _Py_atomic_address;
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typedef struct _Py_atomic_int {
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volatile int _value;
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} _Py_atomic_int;
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#if defined(_M_X64)
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#define _Py_atomic_store_64bit(ATOMIC_VAL, NEW_VAL, ORDER) \
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switch (ORDER) { \
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case _Py_memory_order_acquire: \
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_InterlockedExchange64_HLEAcquire((__int64 volatile*)&((ATOMIC_VAL)->_value), (__int64)(NEW_VAL)); \
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break; \
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case _Py_memory_order_release: \
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_InterlockedExchange64_HLERelease((__int64 volatile*)&((ATOMIC_VAL)->_value), (__int64)(NEW_VAL)); \
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break; \
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default: \
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_InterlockedExchange64((__int64 volatile*)&((ATOMIC_VAL)->_value), (__int64)(NEW_VAL)); \
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break; \
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}
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#else
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#define _Py_atomic_store_64bit(ATOMIC_VAL, NEW_VAL, ORDER) ((void)0);
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#endif
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#define _Py_atomic_store_32bit(ATOMIC_VAL, NEW_VAL, ORDER) \
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switch (ORDER) { \
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case _Py_memory_order_acquire: \
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_InterlockedExchange_HLEAcquire((volatile long*)&((ATOMIC_VAL)->_value), (int)(NEW_VAL)); \
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break; \
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case _Py_memory_order_release: \
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_InterlockedExchange_HLERelease((volatile long*)&((ATOMIC_VAL)->_value), (int)(NEW_VAL)); \
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break; \
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default: \
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_InterlockedExchange((volatile long*)&((ATOMIC_VAL)->_value), (int)(NEW_VAL)); \
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break; \
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}
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#if defined(_M_X64)
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/* This has to be an intptr_t for now.
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gil_created() uses -1 as a sentinel value, if this returns
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a uintptr_t it will do an unsigned compare and crash
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*/
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inline intptr_t _Py_atomic_load_64bit_impl(volatile uintptr_t* value, int order) {
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__int64 old;
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switch (order) {
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case _Py_memory_order_acquire:
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{
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do {
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old = *value;
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} while(_InterlockedCompareExchange64_HLEAcquire((volatile __int64*)value, old, old) != old);
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break;
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}
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case _Py_memory_order_release:
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{
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do {
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old = *value;
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} while(_InterlockedCompareExchange64_HLERelease((volatile __int64*)value, old, old) != old);
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break;
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}
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case _Py_memory_order_relaxed:
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old = *value;
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break;
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default:
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{
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do {
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old = *value;
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} while(_InterlockedCompareExchange64((volatile __int64*)value, old, old) != old);
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break;
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}
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}
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return old;
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}
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#define _Py_atomic_load_64bit(ATOMIC_VAL, ORDER) \
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_Py_atomic_load_64bit_impl((volatile uintptr_t*)&((ATOMIC_VAL)->_value), (ORDER))
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#else
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#define _Py_atomic_load_64bit(ATOMIC_VAL, ORDER) ((ATOMIC_VAL)->_value)
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#endif
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inline int _Py_atomic_load_32bit_impl(volatile int* value, int order) {
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long old;
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switch (order) {
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case _Py_memory_order_acquire:
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{
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do {
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old = *value;
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} while(_InterlockedCompareExchange_HLEAcquire((volatile long*)value, old, old) != old);
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break;
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}
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case _Py_memory_order_release:
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{
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do {
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old = *value;
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} while(_InterlockedCompareExchange_HLERelease((volatile long*)value, old, old) != old);
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break;
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}
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case _Py_memory_order_relaxed:
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old = *value;
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break;
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default:
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{
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do {
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old = *value;
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} while(_InterlockedCompareExchange((volatile long*)value, old, old) != old);
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break;
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}
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}
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return old;
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}
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#define _Py_atomic_load_32bit(ATOMIC_VAL, ORDER) \
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_Py_atomic_load_32bit_impl((volatile int*)&((ATOMIC_VAL)->_value), (ORDER))
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#define _Py_atomic_store_explicit(ATOMIC_VAL, NEW_VAL, ORDER) \
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if (sizeof((ATOMIC_VAL)->_value) == 8) { \
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_Py_atomic_store_64bit((ATOMIC_VAL), NEW_VAL, ORDER) } else { \
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_Py_atomic_store_32bit((ATOMIC_VAL), NEW_VAL, ORDER) }
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#define _Py_atomic_load_explicit(ATOMIC_VAL, ORDER) \
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( \
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sizeof((ATOMIC_VAL)->_value) == 8 ? \
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_Py_atomic_load_64bit((ATOMIC_VAL), ORDER) : \
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_Py_atomic_load_32bit((ATOMIC_VAL), ORDER) \
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)
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#elif defined(_M_ARM) || defined(_M_ARM64)
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typedef enum _Py_memory_order {
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_Py_memory_order_relaxed,
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_Py_memory_order_acquire,
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_Py_memory_order_release,
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_Py_memory_order_acq_rel,
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_Py_memory_order_seq_cst
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} _Py_memory_order;
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typedef struct _Py_atomic_address {
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volatile uintptr_t _value;
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} _Py_atomic_address;
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typedef struct _Py_atomic_int {
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volatile int _value;
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} _Py_atomic_int;
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#if defined(_M_ARM64)
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#define _Py_atomic_store_64bit(ATOMIC_VAL, NEW_VAL, ORDER) \
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switch (ORDER) { \
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case _Py_memory_order_acquire: \
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_InterlockedExchange64_acq((__int64 volatile*)&((ATOMIC_VAL)->_value), (__int64)NEW_VAL); \
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break; \
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case _Py_memory_order_release: \
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_InterlockedExchange64_rel((__int64 volatile*)&((ATOMIC_VAL)->_value), (__int64)NEW_VAL); \
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break; \
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default: \
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_InterlockedExchange64((__int64 volatile*)&((ATOMIC_VAL)->_value), (__int64)NEW_VAL); \
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break; \
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}
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#else
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#define _Py_atomic_store_64bit(ATOMIC_VAL, NEW_VAL, ORDER) ((void)0);
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#endif
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#define _Py_atomic_store_32bit(ATOMIC_VAL, NEW_VAL, ORDER) \
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switch (ORDER) { \
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case _Py_memory_order_acquire: \
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_InterlockedExchange_acq((volatile long*)&((ATOMIC_VAL)->_value), (int)NEW_VAL); \
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break; \
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case _Py_memory_order_release: \
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_InterlockedExchange_rel((volatile long*)&((ATOMIC_VAL)->_value), (int)NEW_VAL); \
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break; \
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default: \
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_InterlockedExchange((volatile long*)&((ATOMIC_VAL)->_value), (int)NEW_VAL); \
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break; \
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}
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#if defined(_M_ARM64)
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/* This has to be an intptr_t for now.
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gil_created() uses -1 as a sentinel value, if this returns
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a uintptr_t it will do an unsigned compare and crash
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*/
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inline intptr_t _Py_atomic_load_64bit_impl(volatile uintptr_t* value, int order) {
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uintptr_t old;
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switch (order) {
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case _Py_memory_order_acquire:
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{
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do {
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old = *value;
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} while(_InterlockedCompareExchange64_acq(value, old, old) != old);
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break;
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}
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case _Py_memory_order_release:
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{
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do {
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old = *value;
|
||||
} while(_InterlockedCompareExchange64_rel(value, old, old) != old);
|
||||
break;
|
||||
}
|
||||
case _Py_memory_order_relaxed:
|
||||
old = *value;
|
||||
break;
|
||||
default:
|
||||
{
|
||||
do {
|
||||
old = *value;
|
||||
} while(_InterlockedCompareExchange64(value, old, old) != old);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return old;
|
||||
}
|
||||
|
||||
#define _Py_atomic_load_64bit(ATOMIC_VAL, ORDER) \
|
||||
_Py_atomic_load_64bit_impl((volatile uintptr_t*)&((ATOMIC_VAL)->_value), (ORDER))
|
||||
|
||||
#else
|
||||
#define _Py_atomic_load_64bit(ATOMIC_VAL, ORDER) ((ATOMIC_VAL)->_value)
|
||||
#endif
|
||||
|
||||
inline int _Py_atomic_load_32bit_impl(volatile int* value, int order) {
|
||||
int old;
|
||||
switch (order) {
|
||||
case _Py_memory_order_acquire:
|
||||
{
|
||||
do {
|
||||
old = *value;
|
||||
} while(_InterlockedCompareExchange_acq(value, old, old) != old);
|
||||
break;
|
||||
}
|
||||
case _Py_memory_order_release:
|
||||
{
|
||||
do {
|
||||
old = *value;
|
||||
} while(_InterlockedCompareExchange_rel(value, old, old) != old);
|
||||
break;
|
||||
}
|
||||
case _Py_memory_order_relaxed:
|
||||
old = *value;
|
||||
break;
|
||||
default:
|
||||
{
|
||||
do {
|
||||
old = *value;
|
||||
} while(_InterlockedCompareExchange(value, old, old) != old);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return old;
|
||||
}
|
||||
|
||||
#define _Py_atomic_load_32bit(ATOMIC_VAL, ORDER) \
|
||||
_Py_atomic_load_32bit_impl((volatile int*)&((ATOMIC_VAL)->_value), (ORDER))
|
||||
|
||||
#define _Py_atomic_store_explicit(ATOMIC_VAL, NEW_VAL, ORDER) \
|
||||
if (sizeof((ATOMIC_VAL)->_value) == 8) { \
|
||||
_Py_atomic_store_64bit((ATOMIC_VAL), (NEW_VAL), (ORDER)) } else { \
|
||||
_Py_atomic_store_32bit((ATOMIC_VAL), (NEW_VAL), (ORDER)) }
|
||||
|
||||
#define _Py_atomic_load_explicit(ATOMIC_VAL, ORDER) \
|
||||
( \
|
||||
sizeof((ATOMIC_VAL)->_value) == 8 ? \
|
||||
_Py_atomic_load_64bit((ATOMIC_VAL), (ORDER)) : \
|
||||
_Py_atomic_load_32bit((ATOMIC_VAL), (ORDER)) \
|
||||
)
|
||||
#endif
|
||||
#else /* !gcc x86 !_msc_ver */
|
||||
typedef enum _Py_memory_order {
|
||||
_Py_memory_order_relaxed,
|
||||
_Py_memory_order_acquire,
|
||||
_Py_memory_order_release,
|
||||
_Py_memory_order_acq_rel,
|
||||
_Py_memory_order_seq_cst
|
||||
} _Py_memory_order;
|
||||
|
||||
typedef struct _Py_atomic_address {
|
||||
uintptr_t _value;
|
||||
} _Py_atomic_address;
|
||||
|
||||
typedef struct _Py_atomic_int {
|
||||
int _value;
|
||||
} _Py_atomic_int;
|
||||
/* Fall back to other compilers and processors by assuming that simple
|
||||
volatile accesses are atomic. This is false, so people should port
|
||||
this. */
|
||||
#define _Py_atomic_signal_fence(/*memory_order*/ ORDER) ((void)0)
|
||||
#define _Py_atomic_thread_fence(/*memory_order*/ ORDER) ((void)0)
|
||||
#define _Py_atomic_store_explicit(ATOMIC_VAL, NEW_VAL, ORDER) \
|
||||
((ATOMIC_VAL)->_value = NEW_VAL)
|
||||
#define _Py_atomic_load_explicit(ATOMIC_VAL, ORDER) \
|
||||
((ATOMIC_VAL)->_value)
|
||||
#endif
|
||||
|
||||
/* Standardized shortcuts. */
|
||||
#define _Py_atomic_store(ATOMIC_VAL, NEW_VAL) \
|
||||
_Py_atomic_store_explicit((ATOMIC_VAL), (NEW_VAL), _Py_memory_order_seq_cst)
|
||||
#define _Py_atomic_load(ATOMIC_VAL) \
|
||||
_Py_atomic_load_explicit((ATOMIC_VAL), _Py_memory_order_seq_cst)
|
||||
|
||||
/* Python-local extensions */
|
||||
|
||||
#define _Py_atomic_store_relaxed(ATOMIC_VAL, NEW_VAL) \
|
||||
_Py_atomic_store_explicit((ATOMIC_VAL), (NEW_VAL), _Py_memory_order_relaxed)
|
||||
#define _Py_atomic_load_relaxed(ATOMIC_VAL) \
|
||||
_Py_atomic_load_explicit((ATOMIC_VAL), _Py_memory_order_relaxed)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* Py_INTERNAL_ATOMIC_H */
|
||||
|
|
@ -8,6 +8,8 @@ extern "C" {
|
|||
# error "this header requires Py_BUILD_CORE define"
|
||||
#endif
|
||||
|
||||
#include "dynamic_annotations.h" // _Py_ANNOTATE_RWLOCK_CREATE
|
||||
|
||||
#include "pycore_interp.h" // PyInterpreterState.eval_frame
|
||||
#include "pycore_pystate.h" // _PyThreadState_GET()
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@ extern "C" {
|
|||
# error "this header requires Py_BUILD_CORE define"
|
||||
#endif
|
||||
|
||||
#include "dynamic_annotations.h" // _Py_ANNOTATE_PURE_HAPPENS_BEFORE_MUTEX
|
||||
|
||||
// Get _POSIX_THREADS and _POSIX_SEMAPHORES macros if available
|
||||
#if (defined(HAVE_UNISTD_H) && !defined(_POSIX_THREADS) \
|
||||
&& !defined(_POSIX_SEMAPHORES))
|
||||
|
|
|
|||
|
|
@ -1754,7 +1754,6 @@ PYTHON_HEADERS= \
|
|||
$(srcdir)/Include/internal/pycore_ast.h \
|
||||
$(srcdir)/Include/internal/pycore_ast_state.h \
|
||||
$(srcdir)/Include/internal/pycore_atexit.h \
|
||||
$(srcdir)/Include/internal/pycore_atomic.h \
|
||||
$(srcdir)/Include/internal/pycore_bitutils.h \
|
||||
$(srcdir)/Include/internal/pycore_bytes_methods.h \
|
||||
$(srcdir)/Include/internal/pycore_bytesobject.h \
|
||||
|
|
|
|||
|
|
@ -202,7 +202,6 @@
|
|||
<ClInclude Include="..\Include\internal\pycore_ast.h" />
|
||||
<ClInclude Include="..\Include\internal\pycore_ast_state.h" />
|
||||
<ClInclude Include="..\Include\internal\pycore_atexit.h" />
|
||||
<ClInclude Include="..\Include\internal\pycore_atomic.h" />
|
||||
<ClInclude Include="..\Include\internal\pycore_bitutils.h" />
|
||||
<ClInclude Include="..\Include\internal\pycore_bytes_methods.h" />
|
||||
<ClInclude Include="..\Include\internal\pycore_bytesobject.h" />
|
||||
|
|
|
|||
|
|
@ -534,9 +534,6 @@
|
|||
<ClInclude Include="..\Include\internal\pycore_atexit.h">
|
||||
<Filter>Include\internal</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="..\Include\internal\pycore_atomic.h">
|
||||
<Filter>Include\internal</Filter>
|
||||
</ClInclude>
|
||||
<ClInclude Include="..\Include\internal\pycore_bitutils.h">
|
||||
<Filter>Include\internal</Filter>
|
||||
</ClInclude>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
|
||||
#include "Python.h"
|
||||
#include "pycore_atomic.h" // _Py_ANNOTATE_RWLOCK_CREATE
|
||||
#include "pycore_ceval.h" // _PyEval_SignalReceived()
|
||||
#include "pycore_initconfig.h" // _PyStatus_OK()
|
||||
#include "pycore_interp.h" // _Py_RunGC()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
#include "pycore_interp.h" // _PyInterpreterState.threads.stacksize
|
||||
#include "pycore_pythread.h" // _POSIX_SEMAPHORES
|
||||
#include "pycore_atomic.h" // _Py_ANNOTATE_PURE_HAPPENS_BEFORE_MUTEX
|
||||
|
||||
/* Posix threads interface */
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue