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veryl/testcases
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Taichi Ishitani 71951a01ab fix case that prefix/suffix are not added to clock/reset ports 
(refs: veryl-lang/veryl#1756)
2025-07-07 09:26:58 +09:00
..
filelist add components referenced only as alias target to filelist 2025-07-01 15:15:02 +09:00
map fix case that prefix/suffix are not added to clock/reset ports 2025-07-07 09:26:58 +09:00
sv fix case that prefix/suffix are not added to clock/reset ports 2025-07-07 09:26:58 +09:00
veryl fix wrong emitting location of import delcarations 2025-07-07 00:39:23 +09:00